View MT9V135_916605.PDF datasheet online --- IC-ON-LINE

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products and specifications discussed herein ar e subject to change by aptina without notice. MT9V135: 1/4-inch system-on-a-chip (soc) vga features pdf: 4892883360/ source: 7488170424 aptina imaging reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 1 ?2006 aptina imaging corporation all rights reserved. 1/4-inch system-on-a-chip (soc) vga ntsc and pal cmos digital image sensor MT9V135 for the latest data sheet, refer to aptinas web site: www.aptina.com features ? digitalclarity ? cmos imaging technology ? system-on-a-chip (soc)? completely integrated camera system ? ntsc and pal (true two field) analog composite video output ? low power, interlaced scan cmos image sensor ? itu-r bt.656 parallel output (8-bit, interlaced) ? serial lvds data output ? supports use of external devices for addition of custom overlay graphics ? superior low-light performance ? on-chip image flow processor (ifp) performs sophisticated processing ? color recovery and correction, sharpening, gamma, lens shading correction, and on-the-fly defect correction ? automatic features: auto exposure (ae), auto white balance (awb), auto blac k reference (abr), auto flicker avoidance, auto color saturation, and auto defect identification and correction ?simple two-wire serial programming interface applications ? 900 mhz and 2.4 ghz wireless cameras ? composite video and digital video out cameras ?cctv security cameras ? consumer video products ?smart cameras ? evidence quality cameras ? cameras with the need for active or passive overlay data sheet applicable to silicon revision: rev4 table 1: ordering information part number description MT9V135c12stc 48-pin clcc es (color) MT9V135c12stcd es 48-pin clcc es demo kit (color) MT9V135c12stch es 48-pin clcc es headboard (color) notes: 1. measured at 2.8v, 30 fps, 25c. 2. customers requiring a similar part with greater tem- perature range should consider using the mt9v125. table 2: key performance parameters parameter typical value optical format 1/4-inch (4:3) active imager size 3.63mm(h) x 2.78mm(v) 4.57mm diagonal active pixels 640h x 480v ntsc output 720h x 486v pal output 720h x 576v pixel size 5.6 m x 5.6 m color filter array rgb paired bayer pattern shutter type electronic rolling shutter (ers) maximum data rate/ master clock 13.5 mp/s 27 mhz frame rate (vga 640h x 480v) 30 fps at 27 mhz (ntsc) 25 fps at 27 mhz (pal) integration time 16 sC33ms (ntsc) 16 sC40ms (pal) adc resolution 10-bit, on-chip responsivity 5 v/lux-sec (550nm) pixel dynamic range 70db snr max 39db supply voltage i/o digital 2.5C3.1v (2.8v nominal) core digital 2.5C3.1v (2.8v nominal) analog 2.5C3.1v (2.8v nominal) power consumption 1 operating 320mw standby 0.56mw operating temperature 1 C30c to +70c package 48-pin clcc
pdf: 4892883360/ source: 7488170424 aptina imaging reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 2 ?2006 aptina imaging corporation. all rights reserved. MT9V135: 1/4-inch system-on-a-chip (soc) vga table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 data sheet applicable to silicon revision: rev4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 typical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 detailed architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 sensor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 image flow processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 black level conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 digital gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 test pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 lens shading correction (lc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 interpolation and aperture correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 defect correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 color correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 color saturation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 automatic white balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 auto exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 automatic flicker detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ntsc and pal encoder formats supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 readout formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 three common data configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 sensor core modes and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 readout format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 window start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 window size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 pixel border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 sensor core readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 column mirror image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 row mirror image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 frame rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 blanking calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 to get an aggressive minimum value for the horizontal blanking, the larger of r0x079[15:8] and r0x076[15:8] can be substituted for the r0x07e value in the above equati on. with default settings, this gives a minimum hblank time of 127.valid data signals options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 line_valid signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 integration time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 maximum shutter delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
pdf: 4892883360/ source: 7488170424 aptina imaging reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 3 ?2006 aptina imaging corporation. all rights reserved. MT9V135: 1/4-inch system-on-a-chip (soc) vga table of contents register notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 sensor registers?short descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 sensor core register descriptions?address page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 color pipe register descriptions?address page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 camera control register descriptions?address page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 modes and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 composite video output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 ntsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 pal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 ntsc or pal with external imag e processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 single-ended and differential composite output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 serial (lvds) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 parallel output (dout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 interlaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 progressive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 parallel input (d in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 interlaced modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 true interlaced. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 reset, clocks, and standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 standby pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 floating inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 output data ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 ntsc signal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 package and die dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 appendix a: serial bus description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 two-wire serial interface sam ple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 8-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 8-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
pdf: 4892883360/ source: 7488170424 aptina imaging reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 4 ?2006 aptina imaging corporation. all rights reserved. MT9V135: 1/4-inch system-on-a-chip (soc) vga list of figures list of figures figure 1: functional block diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 2: typical usage configuration with overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: typical configuration without use of overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 4: 48-pin clcc assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 5: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: image capture example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: pixel color pattern detail (top right corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: spatial illustration of image re adout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: ifp block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: MT9V135 in analog composite video mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 12: MT9V135 in sensor stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 13: MT9V135 in overlay output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 14: six pixels in normal and column mirror readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 15: six rows in normal and row mi rror readout modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 16: line_valid formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 17: integration window of each sensor row for ntsc mo de (interlace readout) . . . . . . . . . . . . . . . . . .31 figure 18: internal registers grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 19: single-ended termination?smpte co mpliant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 20: single-ended termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 figure 21: differential connection?smpte-compliant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 22: differential connection?grounded terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 figure 23: differential connection?floating termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 figure 24: lvds serial output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 figure 25: ccir656 8-bit parallel interfac e format for 525/60 (625/50) video systems . . . . . . . . . . . . . . . . . . . .81 figure 26: typical ccir656 vertic al blanking intervals for 525/60 video system. . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 27: typical ccir656 vertic al blanking intervals for 625/50 video system. . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 28: parallel input data timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 figure 29: primary clock relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 30: digital output i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 31: spectral charac teristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 figure 32: 48-pin clcc package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 33: write timing to r0x009?value 0x 0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 figure 34: read timing from r0x009; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 figure 35: write timing to r0x009?value 0x 0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 figure 36: read timing from r0x009; return ed value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 figure 37: serial host clock period and du ty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 38: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 39: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 40: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 figure 41: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 42: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 figure 43: acknowledge signal timing after an 8-bit read from th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
pdf: 4892883360/ source: 7488170424 aptina imaging reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 5 ?2006 aptina imaging corporation. all rights reserved. MT9V135: 1/4-inch system-on-a-chip (soc) vga list of tables list of tables table 1: ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: readout mode register settings ? d out not qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 5: MT9V135 readout modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 6: readout mode register settings ? d out qualified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 7: register address functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 8: blanking minimum values (in sensor stand-alone mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: sensor core registers?address page 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 10: color pipe registers?address space 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 11: camera control registers?address pa ge 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 12: sensor core registers?address page 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 13: color pipe register?address page 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 14: camera control register?address page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 table 15: lvds packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 table 16: serial output data timing values (for extclk = 27 mh z). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 17: field, vertical blanking, eav, an d sav states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 18: field, vertical blanking, eav, an d sav states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 19: parallel input data timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 table 20: standby effect on the output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 table 21: signal state during standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 table 22: output data ordering in dout rgb mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 23: output data ordering in sensor stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 24: data ordering in lvds serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 table 25: digital output i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table 26: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 27: video dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 table 28: digital i/o parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 29: power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 table 30: ntsc signal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 31: two-wire interface id address switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
MT9V135: 1/4-inch system-on-a-chip (soc) vga general description pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 6 ?2006 aptina imaging corporation all rights reserved. general description the aptina MT9V135 is a vga-format, sing le-chip camera cmos active-pixel digital image sensor. it captures high -quality color images at vga resolution and outputs ntsc or pal interlaced composite video an d ccir 656 digital composite video. this vga cmos image sensor features aptina?s breakthrough digitalclarity ? tech- nology?a low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, low-power, and integration advantages of cmos. the sensor is a complete camera-on-a-chip solution. it incorporates sophisticated camera functions on-chip and is programmab le through a simple two-wire serial inter- face. the MT9V135 performs sophisticated processing functions including color recovery, color correction, sharpening, programmable gamma correction, auto black reference clamping, auto exposure, automatic 50/60hz fl icker avoidance, lens shading correction, auto white balance (awb), and on-the-fly defect identification and correction. the MT9V135 outputs interlaced-scan images at 30 or 25 fps, supporting both ntsc and pal video formats. the image data can be output on any one of three output ports: ? composite analog video (support for both single-ended and differential-ended) ? low-voltage differential signalling (lvds) ? ccir 656 interlaced digital video in parallel 8-bit format functional overview the MT9V135 is a fully-automatic, single-chip camera, requiring only a single power supply, lens, and clock source for basic operat ion. output video is streamed through the chosen output port. the MT9V135 internal registers are configured using a two-wire serial interface. the device can be put into a low-power sleep mode by asserting standby and shutting down the clock. output signals can be tri-stated. both tri-stating output signals and entry into standby mode can be achieved th rough two-wire serial interface register writes. the MT9V135 requires an input clock of 27 mhz to support correct ntsc or pal timing. internal architecture internally, the MT9V135 consists of a sensor core and an image flow processor (ifp). the sensor core captures raw images that are then input into the ifp. the ifp is divided in two sections: the color pipe and the camera controller. the color pipe section processes the incoming stream to create interpolat ed, color-corrected output, and the camera controller section controls the sensor core to maintain the desired exposure and color balance. the ifp scales the image and an integrated video encoder generates either ntsc or pal analog composite output. the MT9V135 suppor ts three different output ports: analog composite video out, lvds serial out, and cc ir 656 interlaced digital video in parallel 8-bit format.
MT9V135: 1/4-inch system-on-a-chip (soc) vga functional overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 7 ?2006 aptina imaging corporation all rights reserved. figure 1 shows the major functional blocks of the MT9V135. figure 2 demonstrates an MT9V135 usage scenario. a dsp takes the mt 9v135?s image output, overlays text, and feeds the resulting image back to the mt 9v135 to be output as ntsc or pal. figure 1: functional block diagram figure 2: typical usage configuration with overlay note: the dsp shown is an external device, it is not part of the MT9V135. sram line buffers image flow processor colorpipe image flow processor camera control image data control bus pixel data sclk s data extclk standby v dd / d gnd v aa / a gnd vaapix lens shading correction color interpolation defect correction color correction gamma correction color conversion + formatting auto exposure auto white balance flicker detect/avoid d out [7:0] pixclk frame_valid line_valid control bus sensor control (gains, shutter, etc.) sensor core 640h x 480v 1/4-inch optical format true interlaced readout auto black compensation programmable analog gain programmable exposure 10-bit adc control bus ntsc and pal encoder and dac lvds formatter and driver lvds_out_pos lvds_out_neg dac_out_pos dac_out_neg d in [7:0] din_clk horizontal interpolator 8 dsp image sensor parallel digital signal with overlay (ccir 656) ntsc or pal composite analog output with overlay d in [7:0] d out [7:0] din_clk parallel digital (ccir 656) pixclk 27 mhz oscillator
MT9V135: 1/4-inch system-on-a-chip (soc) vga typical connections pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 8 ?2006 aptina imaging corporation all rights reserved. typical connections figure 3 shows a detailed MT9V135 device co nfiguration. for low-noise operation, the MT9V135 requires separate an alog and digital power supplies. incoming digital and analog ground conductors can be tied together next to the die. power supply voltages v aa (the primary analog voltage) and vaapix (the main voltage to the pixel array) must be tied together to avoid current loss. both power supply rails should be decoupled to ground using high quality (x7r dielectric) capacitors. the MT9V135 requires a single external voltage supply level. figure 3: typical configuration without use of overlay notes: 1. standby can be connected directly to the customers asic controller or to d gnd , depending on the con- trollers capability. 2. a 1.5k resistor value is recommended, but may be greater for slower two-wire speed (for example, 100 kb/s). 3. lvds_enable must be tied high if lvds is to be used. 4. pull down dac_ref with a 2.8k resistor for 1.0v peak-to-peak video output. 5. v aa and vaapix must be tied to the same potential for proper operation. 6. low pass filter (3db attenuation at 4.2 mhz). a gnd 0.1f 0.1f v aa d g nd 1f v dd vaapix 1f a gnd 0.1f 1f v dd power v aa and vaapix 5 power 1.5k 2 1.5k 2 s data sclk reset_bar lvds_enable 3 frame_valid pixclk line_valid d out [7:0] extclk s addr standby 1 1k d gnd a gnd d gnd a gnd v dd v aa vaapix two-wire serial interface master clock standby from controller or digital gnd pedestal ntsc_pal_select horiz_flip dac_neg dac_pos lvds_neg lvds_pos dac_ref 75 2.8k d in [7:0] din_clk d out _lsb[1:0] rsvd 75 75 terminated receiver v dd dac power v dd pll power v dd dac v dd pll 8 2 low pass filter 6
MT9V135: 1/4-inch system-on-a-chip (soc) vga pin assignments pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 9 ?2006 aptina imaging corporation all rights reserved. pin assignments figure 4 shows the location of the pin assignments on the MT9V135. figure 4: 48-pin clcc assignment table 3: pin descriptions pin assignment name type description 17 extclk input master clock in sensor. 19 reset_bar input active low: asynchronous reset. 22 s addr input two-wire serial interface device id selection 1:0xba, 0:0x90. 23 rsvd input must be attached to d gnd . 21 sclk input two-wire serial interface clock. 18 standby input multifunctional signal to control device addressing, power-down, and state functions (covering output enable function). 24 horiz_flip input if 0 at reset: default horizontal setting. if 1 at reset: flips the image readout format in the horizontal direction. 25 ntsc_pal_select input if 0 at reset: default ntsc mode. if 1 at reset: default pal mode. 27 pedestal input if 0 at reset: does not add pedestal to composite video output. if 1 at reset: adds pedestal to composite video output. valid for ntsc only, pull low for pal operation. 1 2 3 4 5 6 44 43 19 20 21 22 23 24 25 26 27 28 29 30 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31 d in [6] d in [5] d in [4] d in [3] d in [2] d in [1] d in [0] din_clk d gnd v dd extclk standby fv lv v dd pll lvds_pos lvds_neg d gnd v dd d ac_pos v dd dac d ac_neg d gnd dac_ref reset_bar s data sclk s addr rsvd horiz_flip ntsc_pal_select lvds_enable pedestal v aa a gnd vaapix d in [7] d out [7] d out [6] d out [5] d out [4] d out [3] d out [2] d out [1] d out [0] d out _lsb1 d out _lsb0 pixclk 48 47 46 45
MT9V135: 1/4-inch system-on-a-chip (soc) vga pin assignments pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 10 ?2006 aptina imaging corporation all rights reserved. notes: 1. all power pins (v dd /v dd dac/v dd pll/v aa /vaapix) must be connected to 2.8v (nominal). power pins cannot be floated. 2. all ground pins (a gnd /d gnd ) must be connected to ground. ground pins cannot be floated. 3. inputs are not tolerant to signal voltages above 3.1v. 4. all unused inputs must be tied to gnd or v dd . 5. v aa and vaapix must be tied to the same potential for proper operation. 26 lvds_enable input active high: enables the lvds output port. must be high if lvds is to be used. 6, 7, 8, 9, 10, 11, 12, 13 d in [7:0] input external data input port selectable at video encoder input. 14 din_clk input d in capture clock. (this clock must be synchronous to extclk.) 20 s data output two-wire serial interface data i/o. 5, 4, 3, 2, 1, 48, 47, 46 d out [7:0] output pixel data output d out 7 (most significant bit [msb]), d out 0 (least significant bit [lsb]). data output [9:2] in sensor stand-alone mode 44 d out _lsb0 output sensor stand-alone mode output 0typically left unconnected for normal soc operation. 45 d out _lsb1 output sensor stand-alone mode output 1typically left unconnected for normal soc operation. 42 frame_valid output active high: frame_valid (fv); indicates active frame. 41 line_valid output active high: line_valid (lv); indicates active pixel. 43 pixclk output pixel clock output. 35 dac_pos output positive video dac output in differential mode. video dac output in single-ended mode. 33 dac_neg output negative video dac output in differential mode. tie to gnd in single-ended mode 31 dac_ref output external reference resistor for video dac. 39 lvds_pos output lvds positive output. 38 lvds_neg output lvds negative output. 29 a gnd supply analog ground. 15, 32, 37 d gnd supply digital ground. 28 v aa supply analog power: 2.5C3.1v (2.8v nominal). 30 vaapix supply pixel array analog power supply: 2.5C3.1v (2.8v nominal). 16, 36 v dd supply digital power: 2.5C3.1v (2.8v nominal). 34 v dd dac supply dac power: 2.5C3.1v (2.8v nominal). 40 v dd pll supply lvds pll power: 2.5C3.1v (2.8v nominal). table 3: pin descriptions (continued) pin assignment name type description
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 11 ?2006 aptina imaging corporation all rights reserved. detailed architecture overview sensor core the sensor consists of a pixel array of 695 x 512, an analog readou t chain, a 10-bit adc with programmable gain and black offset, and timing and control as illustrated in figure 5. figure 5: sensor core block diagram pixel array structure the sensor core pixel array is configured as 695 columns by 512 rows, as shown in figure 6. the first 42 columns and the first 13 rows of pixels are optically black, and can be used to monitor the black level. the last four columns and the last row of pixels are also optically black. figure 6: pixel array description communication bus to ifp 10-bit data to ifp sync signals clock control register analog processing active pixel sensor (aps) array timing and control adc 8 + 2 active border rows 1 black row 13 black rows 42 black columns 4 black columns 8 active border rows 4 active border columns 4+1 active border columns active paired bayer pixel array 640 x 480 no horizontal/vertical flip (not to scale) pixel logical address = (694, 511) pixel logical address = (0, 0)
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 12 ?2006 aptina imaging corporation all rights reserved. the black row data is used internally for th e automatic black level adjustment. however, these black rows can also be read out by se tting the sensor to raw data output mode. there are 649 columns by 498 rows of opti cally-active pixels that include a pixel boundary around the vga (640 x 480) image to avoid boundary effects during color interpolation and correction. the one additional active column and two a dditional active rows are used to enable horizontally and vertically mirrored re adout to start on the same color pixel. figure 7 illustrates the process of capturing the image. the original scene is flipped and mirrored by the sensor optics. sensor readou t starts at the lower right corner. the image is presented in true orientation by the output display. figure 7: image capture example scene (front view) optics image capture image rendering start readout row by row image sensor (rear view) start rasterization process of i ma g e gatheri n g and im age displa y display (front view)
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 13 ?2006 aptina imaging corporation all rights reserved. the sensor core uses a paired rgb bayer color pattern, as shown in figure 8. row pairs consist of the following: rows 0, 1, rows 2, 3, rows 4, 5, and so on. the even-numbered row pairs (0/1, 4/5, and so on) in the active array contain green and red pixels. the odd- numbered row pairs (2/3, 6/7, and so on ) contain blue and green pixels. the odd- numbered columns contain green and blue pixels; even-numbered columns contain red and green pixels. figure 8: pixel color pattern detail (top right corner) output data format the sensor core image data is read out in an interlaced scan order. progressive readout? which is not supported by the color pipe?is an option, but is only intended for raw data output. valid image data is surrounded by horizontal and vertical blanking, shown in figure 9 on page 14. for ntsc output, the horizontal size is stretc hed from 640 to 720 pixels. the vertical size is 243 pixels per field; 240 imag e pixels and 3 dark pixels that are located at the bottom of the image field. for pal output, the horizontal size is also st retched from 640 to 720 pixels. the vertical size is 288 pixels per field; 24 0 image pixels with 24 dark pi xels at the top of the image and 24 dark pixels at the bottom of the image field. black pixels column readout direction . . . ... row readout direction r r g g r r g g b b g g first active border pixel (42, 13) r r g g r r g g b b g g r r g g r r g g b b g g g g b b g g
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 14 ?2006 aptina imaging corporation all rights reserved. figure 9: spatial illustration of image readout p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 2,0 p 2,1 p 2,2 .....................................p 2,n-1 p 2,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-2,0 p m-2,1 .....................................p m-2,n-1 p m-2,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image odd field horizontal blanking vertical even blanking vertical/horizontal blanking p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n p 3,0 p 3,1 p 3,2 .....................................p 3,n-1 p 3,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m+1,0 p m+1,1 ..................................p m+1,n-1 p m+1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image even field horizontal blanking vertical odd blanking vertical/horizontal blanking
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 15 ?2006 aptina imaging corporation all rights reserved. image flow processor the image flow processor (ifp) consists of a color processing pipe line as well as a measurement and control logic block (the camera controller)?see figure 10 on page 16. the stream of raw data from the sensor ente rs the pipeline and undergoes several trans- formations. image stream processing starts with conditioning the black level and applying a digital gain. the lens shading block compensates for signal loss caused by the lens. next, the data is interpolated to recover missing color components for each pixel. the resulting interpolated rgb data passes through the current color correction matrix (ccm), gamma, and saturation corrections, and is formatted for final output. the measurement and control logic continuo usly accumulate image brightness and color statistics. based on these measurements, the ifp calculates updated values for exposure time and sensor analog gains that are sent to the sensor core through the control bus. black level conditioning the sensor core black level calibration works to maintain black pixel values at a constant level, independent of analog gain, reference current, voltage settings, and temperature conditions. if this black level is above zero, it must be reduced before color processing can begin. the black level subtraction block in the ifp re-maps the black level of the sensor to zero prior to lens shading correction. following lens shading correction, the black level addition block provides capability for another black level adjustment. however, for good contrast, this level should be set to zero. digital gain controlled by auto exposure logic, the input digital gain stage amplifies the raw image in low-light conditions (range: x1?x8). test pattern a built-in test pattern generator produces a test image stream that can be multiplexed with the gain stage. the test pattern ca n be selected through register settings (see r0x148). there is another set of test patter ns at the end of the color pipe that can be selected through register r0x19b[5:4]. (see ?register notation? on page 32.)
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 16 ?2006 aptina imaging corporation all rights reserved. figure 10: ifp block diagram sensor core colorpipe camera control d out [7:0] pixclk, frame_valid, line_valid raw bayer bypass y gamma correct + color sat ctl + ycrcb rgb horizontal interpolator rgb to ycrcb rgb ryb + color correction + r/b gain for awb interpolate + aperture correct register kernel sram line buffers defect correction flicker detection black level conditioning; digital gain; test pattern at beginning of ifp; lens correction vga pixel sensor including sensor control logic control registers two-wire serial interface control registers ae awb test pattern at end of ifp; camera interface control registers
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 17 ?2006 aptina imaging corporation all rights reserved. notes: 1. ntsc encoder/dac not shown lens shading correction (lc) inexpensive lenses tend to attenuate image intensity near the edges of pixel arrays. other factors also cause signal and coloration differences across the image. the net result of all these factors is known as lens shading. lens shading correction (lc) compensates for these differences. typically, the profile of lens shading-induced anomalies across the frame is different for each color component. therefore, lc is inde pendently calibrated for the color channels. interpolation and aperture correction a demosaic engine converts the single-color-per-pixel bayer data from the sensor into rgb (10-bit per color channel). the demosaic algorithm analyzes neighboring pixels to generate a best guess for the missing color components. edge sharpness is preserved as much as possible. aperture correction sharpens the image by an adjustable amount. to avoid amplifying noise, sharpening can be programmed to phase out as light levels drop. defect correction this device supports 2d defect correction. in 2d defect detection and correction, pixels with values different from their neighbors by greater than a defined threshold are considered defects unless near the image boundary. the approach is termed 2d, as pixels on neighboring lines as well as neighboring pixels on the same line are considered in both detection and correction. in figure 10 on page 16, the register kernel gathers same color pixels and send the infor- mation to the 2d defect correction engine. color correction to obtain good color rendition and saturati on, it is necessary to compensate for the differences between the spectral characteristic s of the imager color filter array and the spectral response of the human eye. this compensation, also known as color separation, is achieved through linear transformation of the image with a 3 x 3 element color correc- tion matrix. the optimal values for the colo r correction coefficients depend on the spectra of the incident illumination and can be programmed by the user. color saturation control for noise reduction, both color saturation and sharpness enhancement can be set by the user or adjusted automatically by tracking the magnitude of the gains used by the auto exposure algorithm. automatic white balance the MT9V135 has a built-in automatic wh ite balance (awb) algorithm designed to compensate for the effects of changing scene illumination on the color rendition quality. this sophisticated algorithm cons ists of three major submodules: ? a measurement engine (me) performing statistical analysis of the image ? a module selecting the optimal color correction matrix ? a module selecting the analog color channel gains in the sensor core
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 18 ?2006 aptina imaging corporation all rights reserved. while the default algorithm settings are adequa te in most situations, the user can repro- gram base color correction matrices and li mit color channel gains. the awb does not attempt to locate the brightest or grayest el ements in the image; it performs in-depth image analysis to differentiate between changes in predominant spectra of illumination and changes in predominant scene colors. fact ory defaults are suit able for most appli- cations; however, a wide range of algorithm parameters can be overwritten by the user through the serial interface. auto exposure the auto exposure algorithm performs auto matic adjustments to image brightness by controlling exposure time and analog gains in the sensor core, as well as digital gain applied to the image. the algorithm relies on the auto exposure measurement engine that tracks speed and amplit ude changes in the overall luminance of selected windows in the image. backlight compensation is achieved by weighting the luminance in the center of the image higher than the luminance on the periphery. other algorithm features include: fast-fluctuating illumination rejection (time averaging), response-speed control, and controlled sensitivity to small changes. while the default settings are adequate in mo st situations, the user can program target brightness, measurement window, and other pa rameters, as described above. the auto exposure algorithm enables compensation for a broad range of illumination intensities. automatic flicker detection flicker occurs when integration time is not an integer multiple of the period of the light intensity. the automatic flicker detection block does not compensate for the flicker; it reduces flicker occurrence by detecting flicker frequency and adjusting the integration time. for integration times shorter than the light intensity period (10ms for 50hz envi- ronments and 8.33ms for 60hz enviro nments), flicker is unavoidable. gamma correction to achieve more life-like quality in an image, the ifp includes gamma correction and color saturation control. gamma correction operates on the luminance component of the image and enables compensation for nonl inear dependence of the display device output versus the driving signal (for example, monitor brightness versus crt voltage). in addition, gamma correction provides range compression, converting 10-bit lumi- nance input to 8-bit output. pre-gamma imag e processing generate s 10-bit luminance values ranging from 0 to 896. piecewise linear gamma correction utilized in this imager has 10 linear intervals, with end points corresponding to the following input values: xi=0?10 = {0,16,32,64,128,256,384,512,640,768,896} for each input value xi , the user can program the corresponding output value yi. yi values must be monotonically increasing. ntsc and pal encoder formats supported the MT9V135 has an on-chip video encoder to format the data stream for composite video output in the supported ntsc or pal formats. the encoder expects ccir-656 interlaced ntsc or pal data stream input. by default, the input is taken from the on-chip image stream. input can also be taken from the external 8-bit d in [7:0] port for external image processing used with the on-chip video encoder and composite output.
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 19 ?2006 aptina imaging corporation all rights reserved. readout modes ntsc and pal are two of the target output formats for the MT9V135. table 4 identifies registers used to set ntsc or pal modes. notes: 1. see register notation on page 32 for a description of the register notation. 2. r0x115[0] 3. r0x113[7] 4. r0x113[1:0] 5. r0x19b[12] 6. r0x19b[8] 7. r0x19b[7:6] table 5 identifies the readout format, output format, and output ports supported by the MT9V135. this table gives output formats supported by the MT9V135. the ?devware video output mode? column identifies the name used by the aptina devware demon- stration program to execute the readout mode. MT9V135 registers that enable these modes are specified in table 4 on page 19 . table 4: readout mode register settings C d out not qualified when d out is not qualified with fv and lv readout format/ output format/ output port1 ntsc or pal2 hold fv high3 output select mux4 sensor stand- alone mode5 enable rgb6 rgb output format7 output odd field resolution output even field resolution readout format/ output frame resolution interlaced/ ccir656/ dout[7:0] & lvds 0: ntsc 0 0 0 0 0 720 x 244 720 x 243 720 x 487 interlaced/ ccir656/ dout[7:0] & lvds 1: pal 0 0 0 0 0 720 x 288 720 x 288 720 x 576 table 5: MT9V135 readout modes readout formatCoutput format parallel d out composite analog out lvds devware video output mode interlacedCccir656 supported supported supported interlaced/ccir656 interlacedCrgb supported not supported not supported interlaced/rgb interlacedCraw bayer supported not supported not supported interlaced/raw bayer progressiveCraw paired bayer supported not supported not supported progressive/raw paired bayer
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 20 ?2006 aptina imaging corporation all rights reserved. notes: 1. see register notation on page 32 for a description of the register notation. 2. r0x113[7] 3. r0x115[1:0] 4. r0x113[1:0] 5. r0x19b[12] 6. r0x19b[8] 7. r0x19b[7:6] 8. x = dont care readout formats interlaced the default output format, interlaced format, is required for ntsc or pal output. progressive progressive format is used for raw bayer output. output formats itu-r bt.656 and rgb output the MT9V135 can output processed video as a standard itu-r bt.656 (ccir656) stream, an rgb stream, or as unprocessed ba yer data. the itu-r bt.656 stream contains ycbcr 4:2:2 data with fixed em bedded synchronization codes. this output is typically suitable for subsequent display by standa rd video equipment or jpeg/mpeg compres- sion. rgb functionality provid es support for lcd devices. the MT9V135 can be configured to output 16-bit rgb (rgb565), 15-bit rgb (rgb555), and two types of 12-bit rgb (rgb444). re fer to table 22 on page 87 and table 23 on page 87 for details. table 6: readout mode register settings C d out qualified when d out is qualified with fv and lv readout format/ output format/ output port 1 ntsc or pal 2 hold fv high 3 output select mux 4 sensor stand- alone mode 5 enable rgb 6 rgb output format 7 output odd field reso- lution output even field reso- lution output frame reso- lution interlaced/ ccir656/ d out [7:0] & lvds 0: ntsc 1 0 0 0 0 720 x 243 720 x 243 720 x 486 1: pal 1 0 0 0 0 720 x 288 720 x 288 720 x 576 interlaced/ rgb/d out [7:0] x 8 x 2 0 0 0: rgb 565 1: rgb 555 2: rgb 444x 3: rgb x444 720 x 240 720 x 240 720 x 480 interlaced/raw bayer/ d out [9:0] x x 2 1 0 0 648 x 248 648 x 248 648 x 596 progressive/ raw paired bayer/ d out [9:0] x x 2 1 0 0 n/a n/a 648 x 488
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 21 ?2006 aptina imaging corporation all rights reserved. bayer output unprocessed paired bayer data is generate d when bypassing the ifp completely?that is, by simply outputting the sensor-paired bayer stream as usual, using fv, lv, and pixclk to time the data. this mode is called sensor stand-alone mode. output ports composite video output the composite video output dac is external resistor programmable and supports both single-ended and diffe rential output. the dac is driven by the on-chip video encoder output. serial data output the processed image data stream can be output to the lvds output port. parallel output parallel output uses either 8-bit or 10-bit output. eight-bit output is used for itu-r bt.656 and rgb output. ten-bit output is used for raw bayer output.
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 22 ?2006 aptina imaging corporation all rights reserved. three common data configurations figure 11, figure 12 on page 23, and figure 13 on page 24 demonstrate common config- uration methods for the MT9V135. figure 11 shows the most common usage mode. the processed data from the sensor is output in analog composite video (ntsc or pal) and ccir 656 format through the analog and parallel data output ports, respectively. figure 11: MT9V135 in analog composite video mode tv encoder dac test data internal dac ccir 656 output d out [7:0], fv, lv (without overlay) analog composite video (without overlay) lvds lvds _ pos / lvds _ neg 0 2 0 1 1 0 r0x114[15:14] = 0 async fifo r0x19b[ 12 ] = 0 1 0 data flow path sensor ifp encoder preprocessor r0x113[2] = 0 r0x113[1:0] = 0
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 23 ?2006 aptina imaging corporation all rights reserved. figure 12 shows the MT9V135 in sensor stand-alone mode. raw bayer data from the sensor bypasses the ifp to be output directly. only parallel output is available for this mode. figure 12: MT9V135 in sensor stand-alone mode tv encoder dac test data internal dac lvds 0 2 0 1 1 0 async fifo 1 0 data flow path sensor ifp encoder preprocessor sensor raw output n/a n/a r0x19b[12] = 0 r0x113[2] = 0 r0x113[1:0] = 0 r0x114[15:14] = 0
MT9V135: 1/4-inch system-on-a-chip (soc) vga detailed architecture overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 24 ?2006 aptina imaging corporation all rights reserved. figure 13 shows the MT9V135 in overlay output mode that allows the MT9V135 to be configured with an external dsp for text or image overlay. processed sensor data in ccir 656 format is output as parallel data (d out [7-0]). this data is input to a user-supplied dsp that overlays text or graphics on the processed sensor image. dsp outputs ccir 656 image with overlay which is input through the d in port to be multiplexed at the encoder. this encoded data is output as analog composite video (ntsc or pal). figure 13: MT9V135 in overlay output mode tv encoder dac test data internal dac lvds 0 2 0 1 1 0 async fifo 1 0 data flow path ifp encoder preprocessor ccir-656 output d out [7:0], lv, fv (without overlay ) analog composite video (with overlay) lvds_pos/ lvds_neg ccir-656 input d in [7:0] (with overlay) dsp (adds overlay separate function off chip) sensor r0x114[15:14] = 0 r0x113[2] = 0 r0x113[1:0] = 0 r0x19b[12] = 0
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 25 ?2006 aptina imaging corporation all rights reserved. sensor core modes and timing this section provides an overview of usage modes for the MT9V135 sensor core. an overview of typical usage modes for the comp lete MT9V135 is provided in ?modes and timing? on page 76. readout format the sensor core supports two basic readout formats: interlaced and progressive. the interlaced format supports both ntsc and pa l timing. progressive readout is intended for sensor stand-alone mode only (this is due to the paired bayer pattern cfa). window control the window size and position need to be at the default settings for correct ntsc or pal format support. window start the row and column start address of the di splayed image can be set by r0x001 (row start) and r0x002 (column start). window size the default sensor resolution is 640 columns and 480 rows (vga). for ntsc and pal, this is expanded by the horizontal interpol ator module to 720 columns. for proper ntsc or pal operation, use only the default window size. pixel border when r0x020, bits[9:8] are both set, a 4-pixel border will be added around the specified image. when enabled, the row and column widths will be 8 pixels larger than the values programmed in the row and column registers. if the border is enabled but not shown in the image (r0x020[9:8] = 01), the horizontal blan king and vertical blanking values will be 8 pixels larger than the values programmed into the blanking registers. for proper ntsc or pal operation, use only default values in the above mentioned registers. the border is read in an interlaced pattern when in interlaced readout mode. each field has its own interlaced border on top and bottom of the active array.
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 26 ?2006 aptina imaging corporation all rights reserved. sensor core readout modes column mirror image at reset, the horiz_flip input pin is latched into r0x11e[1]. this bit is xored with register rox115[1]. the result determines if horizontal flip is enabled (result = 1) or disabled (result = 0). figure 14 illustrates the readout order of the columns when they are reversed. the starting color is preserved when mirroring the columns. figure 14: six pixels in normal and column mirror readout modes row mirror image by setting r0x020[0] = 1, the readout order of the rows will be reversed, as shown in figure 15. the starting color is preserved when mirroring the rows. figure 15: six rows in normal and row mirror readout modes frame rate control operating mode actual frame rates can be tuned by adjusting various sensor parameters. the sensor registers are in address page 0, some of which are shown in table 7 on page 27. typical settings and parameters for ntsc and pal modes are shown in table 8 on page 27. for a given window size, the blanking regist ers (r0x005, r0x006, r0x011) can be used to set a particular frame rate. g0[9:0] r0[9:0] g1[9:0] r1[9:0] g2[9:0] r2[9:0] g3[9:0] r2[9:0] g2[9:0] r1[9:0] g1[9:0] r0[9:0] line_valid n ormal readout d out [9:0] r everse readout d out [9:0] row0[9:0] row2[9:0] row4[9:0] row6[9:0] row8[9:0] row10[9:0] row12[9:0] row10[9:0] row8[9:0] row6[9:0] row4[9:0] row2[9:0] frame_valid n ormal readout d out [9:0] r everse readout d out [9:0]
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 27 ?2006 aptina imaging corporation all rights reserved. the sensor timing (table 8 on page 27) is show n in terms of pixel clock and master clock cycles. the required master clock frequency is 27 mhz. the vertical blanking and total frame time equations assume that the number of integration rows (r0x009) is less than the number of active rows, plus blanking rows. if this is not the case, the number of inte- gration rows must be used inst ead to determine the frame time. in the MT9V135, the sensor core adds four border pixels all the way around the image, taking the active image size to 648 x 488. this is achieved through th e default of oversize and show border bits set. ntsc mode has 525 rows per frame; pal mo de has 625 rows per frame as enumerated below (all values in rows): (eq 1) ntsc: (eq 2) pal: (eq 3) blanking calculations when calculating blanking, minimum values for horizontal blanking and vertical blanking must be taken into account. tabl e 8 shows minimum values for each register. this is valid for non ntsc or pal modes only. table 7: register address functions register function r0x004 column width, typically 640 in the MT9V135 r0x003 row width, typically 480 in the MT9V135 r0x005 horizontal blanking, default is 210 (units of sensor pixel clocks) r0x006, r0x011 vertical blanking (odd/even), default is 14 (odd), 15 (even) (rows including black rows) table 8: blanking minimum values (in sensor stand-alone mode) parameter minimum horizontal blanking 132 (sensor pixel clocks) vertical blanking 6 + # of dark rows oddfieldactive oddfieldvert icalblanking evenfieldactive evenfieldverticalblanking +++ rowsperframe = ( 4 240 4) 14 (4 240 4) 15 +++++++ 525 = ( 4 240 4) 64 (4 240 4) 65 +++++++ 625 =
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 28 ?2006 aptina imaging corporation all rights reserved. minimum horizontal blanking (in sensor stand-alone mode) the minimum horizontal blanking value is co nstrained by the time used for sampling a row of pixels and the overhead in the row read out. this can be expressed in an equation as: (eq 4) (eq 5) (eq 6) where: (eq 7) (eq 8) with default settings: (eq 9) to get an aggressive minimum value for the horizontal bl anking, the larger of r0x079[15:8] and r0x076[15:8] can be substituted for the r0x07e value in the above equation. wi th default settings, this gi ves a minimum hblank time of 127. valid data signals options line_valid signal by setting bits[15:14] of r0x020, the lv sign al is programmed for three different output formats. the formats shown below illustrate reading out four rows and two vertical blanking rows (figure 16 on page 29). the default line valid format is shown first; continuous lv is shown second. in the last format, the lv signal is exclusive ored (xor ) between the continuous lv signal and the fv signal. hblank(min) (startup overhead sampling time extra cb time dark col time ) +++ = 31 + done_sample/2 + 16 + (22 read_dark_cols ()) = (47 + done_sample/2 + (22 read_dark_cols ) ) = done_sample r0x07e (rounded up to nearest even number) = read_dark_cols r0x22:0, (bit[8]) = hblank(min) (47 + 152/2 + 22) 145 pixclk periods = =
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 29 ?2006 aptina imaging corporation all rights reserved. figure 16: line_valid formats integration time integration time is controlled by r0x009 (shutt er width, in multiples of the row time) and r0x00c (shutter delay, in pixclk_period/2) . r0x00c is used to control sub-row inte- gration times and will only have a visible effect for small values of r0x009. the total inte- gration time, t int, is shown in the equations below (pixclk_period is in terms of master clock periods): (eq 10) where: (eq 11) (eq 12) (eq 13) with default settings for ntsc: (eq 14) with default settings for pal: (eq 15) in this equation, the integration overhead corresponds to the delay between the row reset sequence and the row sample (read) sequence. the integration overhead shown is valid only for the default pixclk_period and default sample (r0x07e) and reset (r0x087) values. default frame_valid line_valid continuous frame_valid line_valid frame_valid frame_valid xor line_valid int t r0x009 row time integration overhead ? shutter delay ? = row time (r0x004 hblank_reg 8(when border is set)) pixclk_period ++ = i ntegration overhead 182 master clock periods = shutter delay r0x00c/2 pixclk_period = int t 470 858 2 () 182 ? 0 ? 806,388 master clock period s == int t 470 864 2 () 182 ? 0 ? 811,978 master clock periods ==
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 30 ?2006 aptina imaging corporation all rights reserved. typically, the value of the shutter width regi ster (r0x009) is limited to the number of rows per frame (which includes vertical blanki ng rows), such that the frame rate is not affected by the integration time. if r0x009 is increased beyond the total number of rows per frame (525 for ntsc, 625 for pal), the sensor will add additional blanking rows as needed and violate the frame time requirement of ntsc and pal. however, the effective value of r0x009 is always limited by the settings in r0x013 and r0x014. a second constraint is that t int must be adjusted to avoid banding in the image caused by light flicker. this means that t int must be a multiple of 1/120 of a second under 60hz flicker, and a multiple of 1/1 00 of a second under 50hz flicker. maximum shutter delay the shutter delay can be used to reduce the integration time. a programmed value of n reduces the integration time by n master clock periods. the maximum shutter delay is set by the row time and the sample time, as shown in the equations below: (eq 16) where: (eq 17) (eq 18) (eq 19) with default settings: (eq 20) (eq 21) if the value in this register exceeds the maximum value given by this equation, the sensor may not generate an image. again, the overhe ad time shown in this equation is only valid for the default pixclk_period, and the default sample (r0x7e:0) and reset (r0x87:0) valuesfigure 17 on page 31, illustrates the integration time for each sensor row versus the shutter width. odd rows are in tegrated first followed by even rows. max shutter delay row time shutter overhead ? = row time (r0x004 hblank_reg) pixclk_period + = shutter overhead (ntsc) 356 master clock periods = shutter overhead (pal) 368 master clock periods = ntsc max shutter delay (858 2) 356 ? 1360 master clock periods == p al max shutter delay (864 2) 368 ? 1360 master clock periods ==
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 31 ?2006 aptina imaging corporation all rights reserved. figure 17: integration window of each sensor row for ntsc mode (interlace readout) note: drawings are not to scale. t (seconds) 0/60 1/60 2/60 3/60 4/60 5/60 6/60 . . . . . . 1 30 x 525 time shift per row integration window of each row when shutter width r0x009[15:0] = 525 shutter delay r0x00c[15:0] = 0 t (seconds) 0/60 1/60 3/60 4/60 5/60 6/60 odd rows even rows . . . . . . integration window of each row when shutter width r0x009[15:0] = 1 shutter delay r0x00c[15:0] = 0 ll 1 30 x 525 row 1 row 496 row 2 row 495 row 3 row 5 odd rows even field vertical blanking 2/60 row1 (first active row) row3 row5 row495 row2 even rows odd field vertical blanking row496
MT9V135: 1/4-inch system-on-a-chip (soc) vga register overview pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 32 ?2006 aptina imaging corporation all rights reserved. register overview the sensor core, color pipe, and camera control registers are grouped in three separate address spaces, shown in figure 18. the register notation is defined in the section below. when accessing the MT9V135 through the two-wire serial interface, the ad dress space (that is the page) must be set prior to accessing the desired register. the page register is sticky once set; it does not change unless overwritten. the address page is located at one of the three address spaces (r0x0f0, r0x1f0, and r0x2f0). register notation the following register address notations are used: ? r:

example: r9:0?shutter width register (register 9) in the sensor page (page 0). used to uniquely specify a register. ? r0x<3 digit hex address> example: r0x105? page 1, aperture correction register (05). same as 0x<2 digit hex address> notation; leading digit signifies page number. ? data format (binary) column key in the register summary tables: ?0 = ?don't care? bit ? d = rw (read or write) bit ? ? = ro (read only) bit figure 18: internal registers grouping register default values the register definition tables contain the po wer-on default values for the bit fields and registers of the MT9V135. modifying these va lues may affect the performance of the MT9V135 in a positive or negative way. see th e individual register descriptions for more detail. the sensor registers are summ arized in table 9 on page 33. the color pipe registers are summarized in table 11 on page 38. the came ra control registers are summarized in table 12 on page 42. image flow processor sensor core registers r0x000? r0x0ff page 0 color pipeline registers r0:1? r0x1ff page 1 camera control registers r0:2? r0x2ff page 2 r0x0f0 r0x1f0 r0x2f0 cp cc
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 33 ?2006 aptina imaging corporation all rights reserved. sensor registers short descriptions register addresses that do not appear in the summary tables are not used by the MT9V135. table 9: sensor core registersaddress page 0 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex) r0:0(r0x000) chip version dddd dddd dddd dddd 4766 (0x129e) r1:0(r0x001) row start 0000 0ddd dddd dddd 21 (0x0015) r2:0(r0x002) column start 0000 0ddd dddd dddd 46 (0x002e) r3:0(r0x003) reserved C 480 (0x01e0) r4:0(r0x004) reserved C 640 (0x0280) r5:0(r0x005) horizontal blanking 00dd dddd dddd dddd 210 (0x00d2) r6:0(r0x006) odd field vertical blanking 0ddd dddd dddd dddd 14 (0x000e) r7:0(r0x007) field height 0000 0000 dddd dddd 240 (0x00f0) r9:0(r0x009) shutter width dddd dddd dddd dddd 262 (0x0106) r10:0(r0x00a) sensor clock control dddd dddd dddd dddd 17 (0x0011) r11:0(r0x00b) extra delay 00dd dddd dddd dddd 0 (0x0000) r12:0(r0x00c) shutter delay 00dd dddd dddd dddd 0 (0x0000) r13:0(r0x00d) reset and standby control dddd dddd dddd dddd 264 (0x0108) r16:0(r0x010) reserved C 0 (0x0000) r17:0(r0x011) even field vertical blanking 0000 0000 0ddd dddd 15 (0x000f) r18:0(r0x012) reserved C 1260 (0x04ec) r19:0(r0x013) reserved C 525 (0x020d) r20:0(r0x014) reserved C 625 (0x0271) r32:0(r0x020) read mode dd00 00dd dd00 dd0d 768 (0x0300) r34:0(r0x022) dark column and row control 0ddd dddd dddd dddd 269 (0x010d) r36:0(r0x024) extra reset dddd dddd dddd dddd 16384 (0x4000) r43:0(r0x02b) green1 gain 0000 dddd dddd dddd 40 (0x0028) r44:0(r0x02c) blue gain 0000 dddd dddd dddd 100 (0x0064) r45:0(r0x02d) red gain 0000 dddd dddd dddd 30 (0x001e) r46:0(r0x02e) green2 gain 0000 dddd dddd dddd 40 (0x0028) r47:0(r0x02f) global gain d000 dddd dddd dddd 40 (0x0028) r48:0(r0x030) row noise dddd dddd dddd dddd 2090 (0x082a) r49:0(r0x031) reserved C 7168 (0x1c00) r50:0(r0x032) reserved C 42 (0x002a) r51:0(r0x033) reserved C 835 (0x0343) r52:0(r0x034) reserved C 49165 (0xc00d) r53:0(r0x035) reserved C 8226 (0x2022) r54:0(r0x036) reserved C 61680 (0xf0f0) r55:0(r0x037) reserved C 0 (0x0000) r56:0(r0x038) reserved C 8194 (0x2002) r59:0(r0x03b) reserved C 22 (0x0016) r60:0(r0x03c) reserved C 6688 (0x1a20) r61:0(r0x03d) reserved C 8222 (0x201e) r62:0(r0x03e) reserved C 8224 (0x2020) r63:0(r0x03f) reserved C 4128 (0x1020)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 34 ?2006 aptina imaging corporation all rights reserved. r64:0(r0x040) reserved C 8204 (0x200c) r65:0(r0x041) reserved C 215 (0x00d7) r66:0(r0x042) reserved C 1943 (0x0797) r67:0(r0x043) reserved C 1040 (0x0410) r88:0(r0x058) reserved C 0 (0x0000) r89:0(r0x059) reserved C 30 (0x001e) r90:0(r0x05a) reserved C 57354 (0xe00a) r91:0(r0x05b) dark green1 frame average 0000 0000 0??? ???? 32 (0x0020) r92:0(r0x05c) dark blue frame average 0000 0000 0??? ???? 34 (0x0022) r93:0(r0x05d) dark red frame average 0000 0000 0??? ???? 31 (0x001f) r94:0(r0x05e) dark green2 frame average 0000 0000 0??? ???? 32 (0x0020) r95:0(r0x05f) black level calibration threshold dddd dddd dddd dddd 8989 (0x231d) r96:0(r0x060) black level calibration control 000d 000d dddd dddd 128 (0x0080) r97:0(r0x061) green1 offset calibration value 0000 000d dddd dddd 36 (0x0024) r98:0(r0x062) blue offset calibration value 0000 000d dddd dddd 38 (0x0026) r99:0(r0x063) red offset calibration value 0000 000d dddd dddd 36 (0x0024) r100:0(r0x064) green2 offset calibration value 0000 000d dddd dddd 37 (0x0025) r112:0(r0x070) reserved C 40023 (0x9c57) r113:0(r0x071) reserved C 40023 (0x9c57) r114:0(r0x072) reserved C 24921 (0x6159) r115:0(r0x073) reserved C 39257 (0x9959) r116:0(r0x074) reserved C 32631 (0x7f77) r117:0(r0x075) reserved C 32376 (0x7e78) r118:0(r0x076) reserved C 39033 (0x9879) r119:0(r0x077) reserved C 30045 (0x755d) r120:0(r0x078) reserved C 39763 (0x9b53) r121:0(r0x079) reserved C 39253 (0x9955) r122:0(r0x07a) reserved C 39511 (0x9a57) r123:0(r0x07b) reserved C 39766 (0x9b56) r124:0(r0x07c) reserved C 40277 (0x9d55) r125:0(r0x07d) reserved C 30044 (0x755c) r126:0(r0x07e) reserved C 157 (0x009d) r127:0(r0x07f) reserved C 40018 (0x9c52) r128:0(r0x080) reserved C 22532 (0x5804) r129:0(r0x081) reserved C 22532 (0x5804) r130:0(r0x082) reserved C 21520 (0x5410) r131:0(r0x083) reserved C 21777 (0x5511) r132:0(r0x084) reserved C 13842 (0x3612) r133:0(r0x085) reserved C 14100 (0x3714) r134:0(r0x086) reserved C 23042 (0x5a02) r135:0(r0x087) reserved C 92 (0x005c) r200:0(r0x0c8) reserved C 0 (0x0000) r240:0(r0x0f0) page map 0000 0000 0000 0ddd 0 (0x0000) r241:0(r0x0f1) bytewise addr dddd dddd dddd dddd 0 (0x0000) table 9: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 35 ?2006 aptina imaging corporation all rights reserved. r245:0(r0x0f5) reserved C 1023 (0x03ff) r246:0(r0x0f6) reserved C 1023 (0x03ff) r247:0(r0x0f7) reserved C 0 (0x0000) r248:0(r0x0f8) reserved C 0 (0x0000) r249:0(r0x0f9) reserved C 11264 (0x2c00) r250:0(r0x0fa) reserved C 0 (0x0000) r251:0(r0x0fb) reserved C 0 (0x0000) r252:0(r0x0fc) reserved C 0 (0x0000) r253:0(r0x0fd) reserved C 0 (0x0000) r255:0(r0x0ff) chip version ???? ???? ???? ???? 4766 (0x129e) table 10: color pipe registersaddress space 1 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit registernumber dec(hex) register description data forma (binary) default value dec(hex) r5:1(r0x105) aperture correction 0000 0000 0000 dddd 11 (0x000b) r6:1(r0x106) operating mode control dddd dddd dddd dddd 25614 (0x640e) r8:1(r0x108) output format control dddd dddd dddd dddd 128 (0x0080) r16:1(r0x110) reserved C 0 (0x0000) r17:1(r0x111) reserved C 3 (0x0003) r18:1(r0x112) reserved C 0 (0x0000) r19:1(r0x113) chip level control 0000 0ddd dd0d dddd 1920 (0x0780) r20:1(r0x114) reserved C 0 (0x0000) r21:1(r0x115) invert latched pins 0000 0000 dddd dddd 0 (0x0000) r22:1(r0x116) reserved C 0 (0x0000) r23:1(r0x117) reserved C 0 (0x0000) r24:1(r0x118) reserved C 0 (0x0000) r25:1(r0x119) reserved C 0 (0x0000) r26:1(r0x11a) reserved C 0 (0x0000) r27:1(r0x11b) reserved C 0 (0x0000) r28:1(r0x11c) reserved C 0 (0x0000) r29:1(r0x11d) lvds control register 00dd dddd dddd dddd 8192 (0x2000) r30:1(r0x11e) latched pin status 0000 0000 ???? ???? 4 (0x0004) r37:1(r0x125) color saturation control 0000 0000 00dd dddd 5 (0x0005) r52:1(r0x134) luma offset [can be used to control brightness] dddd dddd dddd dddd 16 (0x0010) r53:1(r0x135) luma clip dddd dddd dddd dddd 61456 (0xf010) r58:1(r0x13a) reserved C 512 (0x0200) r59:1(r0x13b) black subtraction 0000 0ddd dddd dddd 1046 (0x0416) r60:1(r0x13c) black addition 0000 0ddd dddd dddd 1024 (0x0400) r71:1(r0x147) reserved C 24 (0x0018) r72:1(r0x148) test pattern generator control 0000 0000 dddd dddd 0 (0x0000) r83:1(r0x153) reserved C 7700 (0x1e14) r84:1(r0x154) reserved C 17966 (0x462e) r85:1(r0x155) reserved C 34666 (0x876a) table 9: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 36 ?2006 aptina imaging corporation all rights reserved. r86:1(r0x156) reserved C 47008 (0xb7a0) r87:1(r0x157) reserved C 57548 (0xe0cc) r88:1(r0x158) reserved C 0 (0x0000) r104:1(r0x168) reserved C 17 (0x0011) r128:1(r0x180) lens correction control 0000 0000 0ddd dddd 3 (0x0003) r129:1(r0x181) lens vertical red knee 0 and initial value dddd dddd dddd dddd 60677 (0xed05) r130:1(r0x182) lens vertical red knees 2 and 1 dddd dddd dddd dddd 3804 (0x0edc) r131:1(r0x183) lens vertical red knees 4 and 3 dddd dddd dddd dddd 61193 (0xef09) r132:1(r0x184) lens vertical green knee 0 and initial value dddd dddd dddd dddd 60677 (0xed05) r133:1(r0x185) lens vertical green knees 2 and 1 dddd dddd dddd dddd 3804 (0x0edc) r134:1(r0x186) lens vertical green knees 4 and 3 dddd dddd dddd dddd 61193 (0xef09) r135:1(r0x187) lens vertical blue knee 0 and initial value dddd dddd dddd dddd 60677 (0xed05) r136:1(r0x188) lens vertical blue knees 2 and 1 dddd dddd dddd dddd 3804 (0x0edc) r137:1(r0x189) lens vertical blue knees 4and 3 dddd dddd dddd dddd 61193 (0xef09) r138:1(r0x18a) lens horizontal red knee 0 and initial value dddd dddd dddd dddd 59401 (0xe809) r139:1(r0x18b) lens horizontal red knees 2 and 1 dddd dddd dddd dddd 63732 (0xf8f4) r140:1(r0x18c) lens horizontal red knees 4 and 3 dddd dddd dddd dddd 61428 (0xeff4) r141:1(r0x18d) lens horizontal red knee 5 0000 0000 dddd dddd 2 (0x0002) r142:1(r0x18e) lens horizontal green knee 0 and initial value dddd dddd dddd dddd 59401 (0xe809) r143:1(r0x18f) lens horizontal green knees 2 and 1 dddd dddd dddd dddd 63732 (0xf8f4) r144:1(r0x190) lens horizontal green knees 4 and 3 dddd dddd dddd dddd 61428 (0xeff4) r145:1(r0x191) lens horizontal green knee 5 0000 0000 dddd dddd 2 (0x0002) r146:1(r0x192) lens horizontal blue knee 0 and initial value dddd dddd dddd dddd 59401 (0xe809) r147:1(r0x193) lens horizontal blue knees 2 and 1 dddd dddd dddd dddd 63732 (0xf8f4) r148:1(r0x194) lens horizontal blue knees 4 and 3 dddd dddd dddd dddd 61428 (0xeff4) r149:1(r0x195) lens horizontal blue knee 5 0000 0000 dddd dddd 2 (0x0002) r153:1(r0x199) line counter 000? ???? ???? ???? 80 (0x0050) r154:1(r0x19a) frame counter ???? ???? ???? ???? 423 (0x01a7) r155:1(r0x19b) output format control 2 0ddd dddd dddd dddd 512 (0x0200) r157:1(r0x19d) defect correction control dddd dddd dddd dddd 9390 (0x24ae) r159:1(r0x19f) reserved C 0 (0x0000) r160:1(r0x1a0) reserved C 640 (0x0280) r161:1(r0x1a1) reserved C 640 (0x0280) r162:1(r0x1a2) reserved C 0 (0x0000) r163:1(r0x1a3) reserved C 240 (0x00f0) r164:1(r0x1a4) reserved C 240 (0x00f0) r165:1(r0x1a5) reserved C 0 (0x0000) r166:1(r0x1a6) reserved C 640 (0x0280) r167:1(r0x1a7) reducer horizontal output size resize 0000 0ddd dddd dddd 640 (0x0280) r168:1(r0x1a8) reserved C 0 (0x0000) r169:1(r0x1a9) reserved C 240 (0x00f0) r170:1(r0x1aa) reducer vertical output size resize 0000 0ddd dddd dddd 240 (0x00f0) r171:1(r0x1ab) reserved C 640 (0x0280) r172:1(r0x1ac) reserved C 240 (0x00f0) table 10: color pipe registersaddress space 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit registernumber dec(hex) register description data forma (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 37 ?2006 aptina imaging corporation all rights reserved. r174:1(r0x1ae) reserved C 3081 (0x0c09) r175:1(r0x1af) reducer zoom control 0000 dddd dddd dddd 2048 (0x0800) r180:1(r0x1b4) reserved C 32 (0x0020) r182:1(r0x1b6) lens vertical red knees 6 and 5 dddd dddd dddd dddd 0 (0x0000) r183:1(r0x1b7) lens vertical red knees 8 and 7 dddd dddd dddd dddd 0 (0x0000) r184:1(r0x1b8) lens vertical green knees 6 and 5 dddd dddd dddd dddd 0 (0x0000) r185:1(r0x1b9) lens vertical green knees 8 and 7 dddd dddd dddd dddd 0 (0x0000) r186:1(r0x1ba) lens vertical blue knees 6 and 5 dddd dddd dddd dddd 0 (0x0000) r187:1(r0x1bb) lens vertical blue knees 8 and 7 dddd dddd dddd dddd 0 (0x0000) r188:1(r0x1bc) lens horizontal red knees 7 and 6 dddd dddd dddd dddd 528 (0x0210) r189:1(r0x1bd) lens horizontal red knees 9 and 8 dddd dddd dddd dddd 526 (0x020e) r190:1(r0x1be) lens horizontal red knee 10 0000 0000 dddd dddd 23 (0x0017) r191:1(r0x1bf) lens horizontal green knees 7 and 6 dddd dddd dddd dddd 528 (0x0210) r192:1(r0x1c0) lens horizontal green knees 9 and 8 dddd dddd dddd dddd 526 (0x020e) r193:1(r0x1c1) lens horizontal green knee 10 0000 0000 dddd dddd 23 (0x0017) r194:1(r0x1c2) lens horizontal blue knees 7 and 6 dddd dddd dddd dddd 528 (0x0210) r195:1(r0x1c3) lens horizontal blue knees 9 and 8 dddd dddd dddd dddd 526 (0x020e) r196:1(r0x1c4) lens horizontal blue knee 10 0000 0000 dddd dddd 23 (0x0017) r200:1(r0x1c8) reserved C 7947 (0x1f0b) r201:1(r0x1c9) reserved C 0 (0x0000) r202:1(r0x1ca) reserved C 0 (0x0000) r203:1(r0x1cb) reserved C 0 (0x0000) r204:1(r0x1cc) reserved C 0 (0x0000) r205:1(r0x1cd) reserved C 0 (0x0000) r206:1(r0x1ce) reserved C 0 (0x0000) r207:1(r0x1cf) reserved C 0 (0x0000) r208:1(r0x1d0) reserved C 0 (0x0000) r220:1(r0x1dc) gamma knee y2 and y1 dddd dddd dddd dddd 4101 (0x1005) r221:1(r0x1dd) gamma knee y3 and y4 dddd dddd dddd dddd 22575 (0x582f) r222:1(r0x1de) gamma knee y5 and y6 dddd dddd dddd dddd 39808 (0x9b80) r223:1(r0x1df) gamma knee y7 and y8 dddd dddd dddd dddd 49840 (0xc2b0) r224:1(r0x1e0) gamma knee y9 and y10 dddd dddd dddd dddd 57554 (0xe0d2) r225:1(r0x1e1) gamma knee y0 0000 0000 dddd dddd 0 (0x0000) r226:1(r0x1e2) reserved C 28672 (0x7000) r227:1(r0x1e3) reserved C 45091 (0xb023) r240:1(r0x1f0) page map 0000 0000 0000 0ddd 1 (0x0001) r241:1(r0x1f1) bytewise addr dddd dddd dddd dddd 0 (0x0000) table 10: color pipe registersaddress space 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit registernumber dec(hex) register description data forma (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 38 ?2006 aptina imaging corporation all rights reserved. table 11: camera control registersaddress page 2 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex) r2:2(r0x202) base matrix signs 0000 000d dddd dddd 238 (0x00ee) r3:2(r0x203) color correction matrices scale codes k1-k5 0ddd dddd dddd dddd 14627 (0x3923) r4:2(r0x204) color correction matrices scale codes k6-k9 0000 dddd dddd dddd 1828 (0x0724) r9:2(r0x209) base matrix color correction coefficient k1 0000 0000 dddd dddd 177 (0x00b1) r10:2(r0x20a) base matrix color correction coefficient k2 0000 0000 dddd dddd 51 (0x0033) r11:2(r0x20b) base matrix color correction coefficient k3 0000 0000 dddd dddd 47 (0x002f) r12:2(r0x20c) base matrix color correction coefficient k4 0000 0000 dddd dddd 128 (0x0080) r13:2(r0x20d) base matrix color correction coefficient k5 0000 0000 dddd dddd 240 (0x00f0) r14:2(r0x20e) base matrix color correction coefficient k6 0000 0000 dddd dddd 96 (0x0060) r15:2(r0x20f) base matrix color correction coefficient k7 0000 0000 dddd dddd 20 (0x0014) r16:2(r0x210) base matrix color correction coefficient k8 0000 0000 dddd dddd 164 (0x00a4) r17:2(r0x211) base matrix color correction coefficient k9 0000 0000 dddd dddd 220 (0x00dc) r18:2(r0x212) current color correction ma trix position 0000 0000 0??? ???? 0 (0x0000) r19:2(r0x213) current awb red channel 0000 0000 ???? ???? 140 (0x008c) r20:2(r0x214) current awb blue channel 0000 0000 ???? ???? 157 (0x009d) r21:2(r0x215) delta matrix signs 0000 000d dddd dddd 0 (0x0000) r22:2(r0x216) delta matrix color correction coefficient d1 0000 0000 dddd dddd 0 (0x0000) r23:2(r0x217) delta matrix color correction coefficient d2 0000 0000 dddd dddd 0 (0x0000) r24:2(r0x218) delta matrix color correction coefficient d3 0000 0000 dddd dddd 0 (0x0000) r25:2(r0x219) delta matrix color correction coefficient d4 0000 0000 dddd dddd 0 (0x0000) r26:2(r0x21a) delta matrix color correction coefficient d5 0000 0000 dddd dddd 0 (0x0000) r27:2(r0x21b) delta matrix color correction coefficient d6 0000 0000 dddd dddd 0 (0x0000) r28:2(r0x21c) delta matrix color correction coefficient d7 0000 0000 dddd dddd 0 (0x0000) r29:2(r0x21d) delta matrix color correction coefficient d8 0000 0000 dddd dddd 0 (0x0000) r30:2(r0x21e) delta matrix color correction coefficient d9 0000 0000 dddd dddd 0 (0x0000) r31:2(r0x21f) chroma limits 0000 0000 dddd dddd 160 (0x00a0) r32:2(r0x220) awb luma limits dddd dddd dddd dddd 51220 (0xc814) r33:2(r0x221) manual wb red and blue gains dddd dddd dddd dddd 32896 (0x8080) r34:2(r0x222) red gain awb limits dddd dddd dddd dddd 55648 (0xd960) r35:2(r0x223) blue gain awb limits dddd dddd dddd dddd 55648 (0xd960) r36:2(r0x224) awb ccm adjustment limits 0ddd dddd 0ddd dddd 32512 (0x7f00) r38:2(r0x226) auto exposure horizontal window boundaries dddd dddd dddd dddd 32768 (0x8000) r39:2(r0x227) auto exposure vertical window boundaries dddd dddd dddd dddd 32776 (0x8008) r40:2(r0x228) awb advanced control dddd dddd dddd dddd 61186 (0xef02) r41:2(r0x229) white balance gain wide stability gates dddd dddd dddd dddd 36211 (0x8d73) r42:2(r0x22a) wb zone validity limits dddd dddd dddd dddd 208 (0x00d0) r43:2(r0x22b) auto exposure horizontal center window boundaries dddd dddd dddd dddd 24608 (0x6020) r44:2(r0x22c) auto exposure vertical center window boundaries dddd dddd dddd dddd 24608 (0x6020) r45:2(r0x22d) awb window boundaries dddd dddd dddd dddd 24977 (0x6191) r46:2(r0x22e) auto exposure target and precision control dddd dddd dddd dddd 2106 (0x083a) r47:2(r0x22f) reserved C 56932 (0xde64) r48:2(r0x230) awb red measurement 0000 0000 ???? ???? 123 (0x007b) r49:2(r0x231) awb luminance measurement 0000 0000 ???? ???? 135 (0x0087)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 39 ?2006 aptina imaging corporation all rights reserved. r50:2(r0x232) awb blue measurement 0000 0000 ???? ???? 109 (0x006d) r51:2(r0x233) reserved C 8209 (0x2011) r52:2(r0x234) auto exposure decision frequency 0000 0000 dddd dddd 0 (0x0000) r54:2(r0x236) auto exposure gain limits dddd dddd dddd dddd 40976 (0xa010) r55:2(r0x237) reserved C 128 (0x0080) r56:2(r0x238) reserved C 1088 (0x0440) r57:2(r0x239) reserved C 1716 (0x06b4) r58:2(r0x23a) reserved C 1716 (0x06b4) r59:2(r0x23b) reserved C 1260 (0x04ec) r60:2(r0x23c) reserved C 1278 (0x04fe) r61:2(r0x23d) reserved C 6108 (0x17dc) r62:2(r0x23e) ccm adjustment gain threshold 000d dddd dddd dddd 8191 (0x1fff) r63:2(r0x23f) auto exposure current gain zone ???? ???? ???? ???? 2 (0x0002) r70:2(r0x246) reserved C 55552 (0xd900) r75:2(r0x24b) reserved C 4 (0x0004) r76:2(r0x24c) auto exposure current luma monitor ???? ???? ???? ???? 15488 (0x3c80) r77:2(r0x24d) auto exposure time averaged luma monitor 0000 0000 ???? ???? 59 (0x003b) r79:2(r0x24f) reserved C 169 (0x00a9) r87:2(r0x257) reserved C 525 (0x020d) r88:2(r0x258) reserved C 625 (0x0271) r89:2(r0x259) reserved C 500 (0x01f4) r90:2(r0x25a) reserved C 500 (0x01f4) r91:2(r0x25b) flicker control ?000 0000 0000 0ddd 32770 (0x8002) r92:2(r0x25c) reserved C 4108 (0x100c) r93:2(r0x25d) reserved C 5392 (0x1510) r94:2(r0x25e) base sensor core gain ratios dddd dddd dddd dddd 30789 (0x7845) r95:2(r0x25f) delta sensor core gain ratios dddd dddd dddd dddd 20007 (0x4e27) r96:2(r0x260) delta sensor core gain ratio signs 0000 0000 0000 00dd 2 (0x0002) r97:2(r0x261) awb analog gain ratios monitor ???? ???? ???? ???? 40753 (0x9f31) r98:2(r0x262) auto exposure digital ga in monitor ???? ???? ???? ???? 4112 (0x1010) r99:2(r0x263) reserved C 12330 (0x302a) r100:2(r0x264) reserved C 23036 (0x59fc) r101:2(r0x265) auto exposure luma offset 0000 00dd dddd dddd 0 (0x0000) r103:2(r0x267) auto exposure digital gain limits dddd dddd dddd dddd 8208 (0x2010) r104:2(r0x268) reserved C 17 (0x0011) r106:2(r0x26a) reserved C 0 (0x0000) r107:2(r0x26b) reserved C 0 (0x0000) r108:2(r0x26c) reserved C 126 (0x007e) r109:2(r0x26d) reserved C 126 (0x007e) r110:2(r0x26e) reserved C 62 (0x003e) r111:2(r0x26f) reserved C 126 (0x007e) r112:2(r0x270) reserved C 110 (0x006e) r113:2(r0x271) reserved C 66 (0x0042) r114:2(r0x272) reserved C 66 (0x0042) table 11: camera control registersaddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 40 ?2006 aptina imaging corporation all rights reserved. r115:2(r0x273) reserved C 2 (0x0002) r116:2(r0x274) reserved C 122 (0x007a) r117:2(r0x275) reserved C 114 (0x0072) r118:2(r0x276) reserved C 78 (0x004e) r119:2(r0x277) reserved C 118 (0x0076) r120:2(r0x278) reserved C 94 (0x005e) r121:2(r0x279) reserved C 126 (0x007e) r122:2(r0x27a) reserved C 68 (0x0044) r123:2(r0x27b) reserved C 64 (0x0040) r124:2(r0x27c) reserved C 64 (0x0040) r125:2(r0x27d) reserved C 0 (0x0000) r130:2(r0x282) reserved C 1023 (0x03ff) r131:2(r0x283) reserved C 769 (0x0301) r132:2(r0x284) reserved C 193 (0x00c1) r133:2(r0x285) reserved C 929 (0x03a1) r134:2(r0x286) reserved C 980 (0x03d4) r135:2(r0x287) reserved C 983 (0x03d7) r136:2(r0x288) reserved C 921 (0x0399) r137:2(r0x289) reserved C 1016 (0x03f8) r138:2(r0x28a) reserved C 28 (0x001c) r139:2(r0x28b) reserved C 957 (0x03bd) r140:2(r0x28c) reserved C 987 (0x03db) r141:2(r0x28d) reserved C 957 (0x03bd) r142:2(r0x28e) reserved C 1020 (0x03fc) r143:2(r0x28f) reserved C 990 (0x03de) r144:2(r0x290) reserved C 990 (0x03de) r145:2(r0x291) reserved C 990 (0x03de) r146:2(r0x292) reserved C 990 (0x03de) r147:2(r0x293) reserved C 31 (0x001f) r148:2(r0x294) reserved C 65 (0x0041) r149:2(r0x295) reserved C 867 (0x0363) r150:2(r0x296) reserved C 0 (0x0000) r151:2(r0x297) reserved C 384 (0x0180) r152:2(r0x298) reserved C 255 (0x00ff) r153:2(r0x299) reserved C 1 (0x0001) r156:2(r0x29c) reserved C 57120 (0xdf20) r180:2(r0x2b4) reserved C 32 (0x0020) r181:2(r0x2b5) reserved C 257 (0x0101) r198:2(r0x2c6) reserved C 0 (0x0000) r199:2(r0x2c7) reserved C 0 (0x0000) r200:2(r0x2c8) reserved C 7947 (0x1f0b) r201:2(r0x2c9) reserved C 0 (0x0000) r202:2(r0x2ca) reserved C 43264 (0xa900) r203:2(r0x2cb) reserved C 0 (0x0000) table 11: camera control registersaddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor registersshort descriptions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 41 ?2006 aptina imaging corporation all rights reserved. r204:2(r0x2cc) reserved C 0 (0x0000) r205:2(r0x2cd) reserved C 8608 (0x21a0) r206:2(r0x2ce) reserved C 7835 (0x1e9b) r207:2(r0x2cf) reserved C 19018 (0x4a4a) r208:2(r0x2d0) reserved C 5773 (0x168d) r209:2(r0x2d1) reserved C 77 (0x004d) r210:2(r0x2d2) reserved C 0 (0x0000) r211:2(r0x2d3) reserved C 0 (0x0000) r212:2(r0x2d4) reserved C 520 (0x0208) r213:2(r0x2d5) reserved C 0 (0x0000) r239:2(r0x2ef) reserved C 8 (0x0008) r240:2(r0x2f0) page map 0000 0000 0000 0ddd 2 (0x0002) r241:2(r0x2f1) bytewise addr dddd dddd dddd dddd 0 (0x0000) r242:2(r0x2f2) awb red and blue gains offsets dddd dddd dddd dddd 0 (0x0000) r243:2(r0x2f3) reserved C 685 (0x02ad) r245:2(r0x2f5) reserved C 64 (0x0040) r246:2(r0x2f6) reserved C 127 (0x007f) r247:2(r0x2f7) reserved C 1728 (0x06c0) r248:2(r0x2f8) reserved C 1728 (0x06c0) r249:2(r0x2f9) reserved C 1360 (0x0550) r250:2(r0x2fa) reserved C 1280 (0x0500) r251:2(r0x2fb) reserved C 525 (0x020d) r252:2(r0x2fc) reserved C 625 (0x0271) r253:2(r0x2fd) reserved C 502 (0x01f6) r254:2(r0x2fe) reserved C 502 (0x01f6) r255:2(r0x2ff) reserved C 43136 (0xa880) table 11: camera control registersaddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number dec(hex) register description data format (binary) default value dec(hex)
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 42 ?2006 aptina imaging corporation all rights reserved. sensor core register descriptionsaddress page 0 table 12: sensor core registersaddress page 0 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame r0:0 r0x000 15:0 0x129e chip version (ro) 15:8 0x0012 reserved 7:4 0x0009 reserved 3 0x0001 reserved 2:0 0x0006 reserved chip version. read only r1:0 r0x001 15:0 0x0015 row start (r/w) y n the first row of the output frame. a value of 21 (default value) starts the output frame at the first active row. changing this register is not advised since the image would be moved out of the visible area. r2:0 r0x002 15:0 0x002e column start (r/w) n n the first column of the output frame. a value of 46 (default value) starts the output frame at the first active column; use onl y the default value for correct ntsc or pal operation. r5:0 r0x005 15:0 0x00d2 horizontal blanking (r/w) y n number of blank columns in a row. use only the default values for correct ntsc or pal operation. default for ntsc: 0xd2; pal: 0xd8. r6:0 r0x006 15:0 0x000e odd field vertical blanking (r/w) n n number of rows in the odd vertical blanking period. use only the default values for correct ntsc or pal operation. default for ntsc: 0x0e; pal: 0x40. r7:0 r0x007 15:0 0x00f0 field height (r/w) n y field height in rows. one half the pixel array image rows, output in each field for ntsc or pal operation modes. default value set to 240. use only the default value for correct ntsc or pal operation. r9:0 r0x009 15:0 0x0106 shutter width (r/w) y n integration time in number of rows. the total integration time is also influenced by the shutter delay (r12:0) and the integration-overhead time. r10:0 r0x00a 15:0 0x0011 sensor clock control (r/w) 15:14 0x0000 reserved 13 0x0000 reserved 12:9 x reserved 8 0x0000 invert pixel clock for soc bypass mode only. 0: frame_valid, line_valid, and dout are set up relative to the delayed rising edge of pixclk. 1: frame_valid, line_valid, and dout are set up relative to the delayed falling edge of pixclk. nn 7:4 0x0001 reserved 3:0 0x0001 reserved r11:0 r0x00b 15:0 0x0000 extra delay (r/w) n n extra vertical blanking inserted between frames. a programmed value of n increases the vertical blanking time by n pixel clock periods. can be used to get a more exact frame rate. it may affect the integration times of parts of the image when the integration time is less than one frame. use only the default value for correct ntsc and pal operation.
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 43 ?2006 aptina imaging corporation all rights reserved. r12:0 r0x00c 15:0 0x0000 shutter delay (r/w) n n the amount of time from the end of the sampling sequence to the beginning of the pixel reset sequence. if the value in this register exceeds the row time, the reset of the row does not co mplete before the associated row is sampled, and the sensor does not generate an image. a programmed value of n reduces the integration time by n pixel clock periods. r13:0 r0x00d 15:0 0x0108 reset and standby control (r/w) 15 0x0000 synchronize changes 0: default operation, updates changes to registers that affect image brightness at the next frame boundary (integration time, integration delay, gain, horizontal blanking and vertical blanking, or row mirror). 1: inhibits this update; register changes remain pending until this bit is returned to 0. when this bit is returned to 0, all pending register updates are made on the next frame start. nn 14 x reserved 13 0x0000 stop soc 0: soc clocks are enabled. 1: soc clocks are disabled. nn 12 0x0000 reserved 11 x reserved 10 0x0000 toggle two-wire serial interface address 0: by default, the sensor serial bus responds to addresses 0xba and 0xbb. 1: the sensor serial bus responds to addresses 0x90 and 0x91. writes to this bit are ignored when standby is asserted. see slave address on page 95. nn 9 0x0000 restart bad frames 0: no restart is forced for bad frames. 1: a restart is forced to take place whenever a bad frame is detected. this can shorten the delay when waiting for a good frame since the delay, when masking out a bad frame and performing a restart, is the integration time rather than the full frame time. nn 8 0x0001 show bad frames 0: only output good frames (default). 1: output all frames (including bad frames). a bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, pixel clock speed, mirroring, or use of border. nn 7 0x0000 inhibit standby from pin by default, asserting the standby pin places the sensor in a low-power state. 0: normal operation. 1: stops the standby pin from affecting entry to or exit from the low-power state. see power-saving modes on page 86. nn 6 0x0000 standby output enable 0: asserting standby causes the pin interface to enter a high-z (default). 1: stops standby from contributing to output-enable control. nn 5 0x0000 reset soc registers 0: resume the soc. 1: reset to soc (only). nn table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 44 ?2006 aptina imaging corporation all rights reserved. 4 0x0000 output disable 0: normal operation. 1: output signals are tri-stated. nn 3 0x0001 chip enable 0: stop sensor readout. when this is returned to 1, sensor readout restarts and begins resetting the starting row in a new frame. to reduce the digital power, the master clock to the sensor can be disabled or the standby pin can be used. 1: normal operation. nn 2 0x0000 analog standby 0: normal operation 1: place the sensor in a low-power state. see power-saving modes on page 86. note: setting this bit will effect ntsc and pal operation. nn 1 0x0000 restart sensor 0: normal operation. 1: causes the sensor to truncate the current frame and start resetting the first row. the delay before the first valid frame is read out is equal to the integration time. this bit always reads back as 0. nn 0 0x0000 reset registers 0: resume normal operation 1: puts the sensor in reset; the frame being generated is truncated and the pin interface goes to an idle state. all internal registers (except for this bit) go to the default power-up state. nn r17:0 r0x011 15:0 0x000f even field vertical blanking (r/w) y n vertical blanking in rows, between two fields in interlaced modes (ntsc or pal). to keep correct ntsc or pal timing, this register must be programmed with the default values. default for ntsc: 0x0f; pal: 0x41. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 45 ?2006 aptina imaging corporation all rights reserved. r32:0 r0x020 15:0 0x0300 read mode (r/w) 15 0x0000 xor line_valid with frame_valid 0: line_valid = line_valid 1: xor line_valid with frame_valid nn 14 0x0000 line_valid during vertical blanking 0: normal line_valid (default, no line_valid during vertical blank). 1: continuous line_valid (continue producing line_valid during vertical blanking). nn 13:10 x reserved 9 0x0001 show border 0: do not show the border. 1: this bit indicates whether to show the border enabled by bit 8. when bit 8 is 0, this bit has no meaning. when bit 8 is 1, this bit decides whether the border pixels should be treated as extra active pixels (1) or extra blanking pixels (0). must be set for correct ntsc and pal operation. nn 8 0x0001 readout border pixels 0: do not read out border pixels. 1: a 4-pixel border is output around the active image array independent of readout mode (mirror and so forth). setting this bit therefore adds 4 to the numbers of rows and columns in the frame. must be set for correct ntsc and pal operation. nn 7 0x0000 reserved 6 0x0000 reserved 5:4 x reserved 3 0x0000 first field even in pal mode 0: the first pal field output consists of odd-numbered rows of the pixel array, and the second field consists of even-numbered rows. 1: the first pal field output consists of even-numbered rows of pixel the array, and the second field consists of odd-numbered rows. nn 2 0x0000 first field even in ntsc mode 0: the first ntsc field output consists of odd-numbered rows of the pixel array. the second field consists of even-numbered rows. 1: the first ntsc field output consists of even-numbered rows of pixel array. the second field consists of odd-numbered rows. nn 1xreserved 0 0x0000 mirror rows 0: rows not mirrored (sensor reads top to bottom). 1: rows mirrored (image flipped vertically, sensor reads bottom to top). to mirror columns (horizontal flip), see r21:1 bit 1. nn bit 0, mirrors row read. the rows are read from highest value (bottom) to lowest (top). bits 8 and 9 enable the sensor logic to read the border pixels and show them. for correct pal or ntsc operation, these bits must be set (default). table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 46 ?2006 aptina imaging corporation all rights reserved. r34:0 r0x022 15:0 0x010d dark column and row control (r/w) 15:10 x reserved 9 0x0000 show dark columns in output frame 0: do not show dark columns. 1: the programmed dark columns are output before the active pixels in a line. the dark columns are usually read out during horizontal blank. the horizontal blanking time is therefore decreased by the same amount that is added to the active line when this bit is enabled. this feature does not work in the ntsc and pal output modes. nn 8 0x0001 read dark columns 0: an arbitrary number of dark columns can be read out by including them in the active image. 1: enables the readout of dark columns 23:4 for use in the row-wise noise correction algorithm. enabling the dark columns increases the minimum value for horizontal blanking but does not affect the row time. nn 7 0x0000 show dark rows in output frame 0: do not show dark rows. 1: the programmed dark rows are output before the active window along with the extra rows between the dark and active rows. frame_valid is thus asserted earlier than normal. this has no effect on integration time or frame rate. this feature does not work in the ntsc and pal output modes. nn 6:4 0x0000 reserved 3 0x0001 reserved 2:0 0x0005 reserved when bit 7 is set, dark and extra rows (always 2) are shown. bit 8 and 9 decide if the dark columns are to be read and shown, respectively. r36:0 r0x024 15:0 0x4000 extra reset (r/w) 15 x reserved 14 0x0001 reset next row n n 13:0 x reserved setting bit 14 enables the next row reset logic. when enabled, th e sensor logic resets also the next row to the row being reset by the shutter operation, when it is applicable. note that in interlaced modes, the next row belongs to the next field. the condition is that the shutter width is less than one field time. r43:0 r0x02b 15:0 0x0028 green1 gain (r/w) 15:12 x reserved 11:9 0x0000 digital gain total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*analog gain nn 8:7 0x0000 analog gain analog gain = [bit8 +1]*[bit7 +1]*initial gain nn 6:0 0x0028 initial gain initial gain = bits[6:0] * 0.03125. a value of 32 corresponds to a gain of 1.0. nn the initial analog gain is equal to the value in bits [6:0] multiplied by 0.03125 (1/32). for each 1 in the bits 7 and 8, the total gain is doubled. bits [11:9] are used in the sensor logic; for each 1 in these bits, the data from the adc is doubled (that is, the total gain is doubled). total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*[bit8 +1]*[bit7 +1]*initial gain. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 47 ?2006 aptina imaging corporation all rights reserved. r44:0 r0x02c 15:0 0x0064 blue gain (r/w) 15:12 x reserved 11:9 0x0000 digital gain total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*analog gain nn 8:7 0x0000 analog gain analog gain = [bit8 +1]*[bit7 +1]*initial gain nn 6:0 0x0064 initial gain initial gain = bits[6:0] * 0.03125. a value of 32 corresponds to a gain of 1.0. nn the initial analog gain is equal to the value in bits [6:0] multiplied by 0.03125 (1/32). for each 1 in the bits 7 and 8, the total gain is doubled. bits [11:9] are used in the sensor logic; for each 1 in these bits, the data from the adc is doubled (that is, the total gain is doubled). total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*[bit8 +1]*[bit7 +1]*initial gain. r45:0 r0x02d 15:0 0x001e red gain (r/w) 15:12 x reserved 11:9 0x0000 digital gain total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*analog gain nn 8:7 0x0000 analog gain analog gain = [bit8 +1]*[bit7 +1]*initial gain nn 6:0 0x001e initial gain initial gain = bits[6:0] * 0.03125. a value of 32 corresponds to a gain of 1.0. nn the initial analog gain is equal to the value in bits [6:0] multiplied by 0.03125 (1/32). for each 1 in the bits 7 and 8, the total gain is doubled. bits [11:9] are used in the sensor logic; for each 1 in these bits, the data from the adc is doubled (that is, the total gain is doubled). total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*[bit8 +1]*[bit7 +1]*initial gain. r46:0 r0x02e 15:0 0x0028 green2 gain (r/w) 15:12 x reserved 11:9 0x0000 digital gain total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*analog gain nn 8:7 0x0000 analog gain analog gain = [bit8 +1]*[bit7 +1]*initial gain nn 6:0 0x0028 initial gain initial gain = bits[6:0] * 0.03125. a value of 32 corresponds to a gain of 1.0. nn the initial analog gain is equal to the value in bits [6:0] multiplied by 0.03125 (1/32). for each 1 in the bits 7 and 8, the total gain is doubled. bits [11:9] are used in the sensor logic; for each 1 in these bits, the data from the adc is doubled (that is, the total gain is doubled). total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*[bit8 +1]*[bit7 +1]*initial gain. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 48 ?2006 aptina imaging corporation all rights reserved. r47:0 r0x02f 15:0 0x0028 global gain (r/w) 15 0x0000 reserved 14:12 x reserved 11:9 0x0000 digital gain total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*analog gain nn 8:7 0x0000 analog gain analog gain = [bit8 +1]*[bit7 +1]*initial gain nn 6:0 0x0028 initial gain initial gain = bits[6:0] * 0.03125. a value of 32 corresponds to a gain of 1.0. nn writing a value to this register is equal to writing that value to the 4 gain registers: 0x2b:0, 0x2c:0, 0x2d:0 and 0x2e:0. whe n read, it returns the value stored in reg0x2b:0. the initial analog gain is equal to the value in bits [6:0] multiplied by 0.03125 (1/32). for each 1 in the bits 7 and 8, the total gain is doubled. bits [11:9] are used in the sensor logic; for each 1 in these bits , the data from the adc is doubled (that is, the total gain is doubled). total gain = [bit11 +1]*[bit10 +1]*[bit9 +1]*[bit8 +1]*[bit7 +1]*initial gain. r48:0 r0x030 15:0 0x082a row noise (r/w) 15 0x0000 enable digital frame-wise correction when this bit is set, the black level is calculated and applied for each color of each of the four black rows and the same values are applied to each subsequent row so that new values are applied once per frame. nn 14:12 0x0000 gain threshold when the upper analog gain bits are equal to or larger than this threshold, the dark column average is used in the row noise correction algorithm. otherwise, the subtracted value is determined by r48:0[11]. this check is performed independently for each color, and is a means to turn off the row noise correction algorithm for lower gains without affecting the black level out of the sensor. typical threshold values are 0, 1, 3 and 7. (0 - x1/32 - x1/16; 1 - x2 - x16; 3 - x4 - x16; 7 - x8 - x16). nn 11 0x0001 use black level average 0: use the mean of the black level programmed threshold in the row noise correction algorithm for low gains. 1: use the black level frame average from the dark rows in the row noise correction algorithm for low gains. note: this frame average was taken before the last adjustment of the offset dac for that frame, so it might be slightly off. nn 10 0x0000 enable correction 0: normal operation. 1: enable row noise cancellation algorithm. the average value of the dark columns read out is used as a correction for the whole row. the dark average is subtracted from each pixel on the row, and then a constant is added (r48:0[9:0]). nn 9:0 0x002a row noise constant constant used in the row noise cancellation algorithm. it should be set to the dark level targeted by the black level algorithm plus the noise expected between the averaged values of the dark columns. the default constant is set to 42 lsb. nn r91:0 r0x05b 15:0 0x0020 dark green1 frame average (ro) n n the frame-averaged green1 black level that is used in the black level calibration algorithm. r92:0 r0x05c 15:0 0x0022 dark blue frame average (ro) n n the frame-averaged blue black level that is used in the black level calibration algorithm. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 49 ?2006 aptina imaging corporation all rights reserved. r93:0 r0x05d 15:0 0x001f dark red frame average (ro) n n the frame-averaged red black level that is used in the black level calibration algorithm. r94:0 r0x05e 15:0 0x0020 dark green2 frame average (ro) n n the frame-averaged green2 black level that is used in the black level calibration algorithm. r95:0 r0x05f 15:0 0x231d black level calibration threshold (r/w) 15 x reserved 14:8 0x0023 thres_hi upper threshold for targeted black level in adc lsbs. nn 7x reserved 6:0 0x001d thres_lo lower threshold for targeted black level in adc lsbs. nn r96:0 r0x060 15:0 0x0080 black level calibration control (r/w) 15:9 x reserved 8 0x0000 enable calibration sweep mode 0: disable calibration sweep mode 1: the calibration value is increased by one every frame, and all channels are the same. this can be used to get a ramp input to the adc from the calibration dacs. nn 7:5 0x0004 frames to average over 2 to the power of this value determines how many frames to average when the black level algorithm is in the averaging mode. in this mode, the running frame average is calculated from the following formula: running frame ave = old running frame ave - (old running frame ave)/2n + (new frame ave)/ 2n. nn 4 0x0000 keep step size at 1 0: start at a higher step size when in rapid sweep mode, to converge faster to the correct value. (default) 1: the step size is forced to 1 for the rapid sweep algorithm. nn 3 0x0000 reserved 2 0x0000 use red calib value for blue 1: the same calibration value is used for red and blue pixels: calib blue = calib red. nn 1 0x0000 use green1 calib value for green2 1: the same calibration value is used for all green pixels: calib green2 = calib green1. nn 0 0x0000 manual override auto black level manual override of black level correction. 0: normal operation (default). 1: override automatic black level correction with programmed values. (r0x61:0 to r0x64:0). nn r97:0 r0x061 15:0 0x0024 green1 offset calibration value (r/w) n n analog calibration offset for green1 pixels, represented as a two's complement 8-bit value (range: -256 to 255). if r0x60:0[0] = 0, this register is ro and returns the current value computed by the black level calibration algorithm. if r0x60:0[0] = 1, this register is r/w and can be used to se t the calibration offset manually. green1 pixels share rows with r ed pixels. r98:0 r0x062 15:0 0x0026 blue offset calibration value (r/w) n n analog calibration offset for blue pixels, represented as a two's complement 8-bit value (range: -256 to 255). if r0x60:0[0] = 0, this register is ro and returns the current value computed by the black level calibration algorithm. if r0x60:0[0] = 1, this register is r/w and can be used to set the calibration offset manually. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga sensor core register descriptionsaddress page 0 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 50 ?2006 aptina imaging corporation all rights reserved. r99:0 r0x063 15:0 0x0024 red offset calibration value (r/w) n n analog calibration offset for red pixels, represented as a two's complement 8-bit value (range: -256 to 255). if r0x60:0[0] = 0, this register is ro and returns the current value computed by the black level calibration algorithm. if r0x60:0[0] = 1, this register is r/w and can be used to manually set the calibration offset. r100:0 r0x064 15:0 0x0025 green2 offset calibration value (r/w) n n analog calibration offset for green2 pixels, represented as a two's complement 8-bit value (range: -256 to 255). if r0x60:0[0] = 0, this register is ro and returns the current value computed by the black level calibration algorithm. if r0x60:0[0] = 1, this register is r/w and can be used to manually set the calibration offset. green2 pixels share rows with blue pixels. r240:0 r0x0f0 15:0 0x0000 page map (r/w) n n set camera chip register page. 0: sensor core 1: colorpipe 2: camera control. r241:0 r0x0f1 15:0 0x0000 bytewise addr (r/w) n n special address to perform 8-bit (instead of 16-bit) reads and writes to the sensor. for additional information, see two- wire serial interface sample on page 96 and appendix a: serial bus description on page 94. r255:0 r0x0ff 15:0 0x129e chip version (ro) n n chip version. read only. table 12: sensor core registersaddress page 0 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name frame sync'd bad frame
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 51 ?2006 aptina imaging corporation all rights reserved. color pipe register descriptionsaddress page 1 table 13: color pipe registeraddress page 1 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name r5:1 r0x105 15:0 0x000b aperture correction (r/w) 15:4 x reserved 3 0x0001 enable auto sharpening enables automatic sharpness reduction control. 2:0 0x0003 sharpening factor sharpening factor: 000: no sharpening. 001: 25% sharpening. 010: 50% sharpening. 011: 75% sharpening. 100: 100% sharpening. 101: 125% sharpening. 110: 150% sharpening. 111: 200% sharpening. aperture correction scale factor used for sharpening.
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 52 ?2006 aptina imaging corporation all rights reserved. r6:1 r0x106 15:0 0x640e operating mode control (r/w) 15 0x0000 manual white balance enables manual white balance. user can set the base matrix and color channel gains. this bit must be asserted and de-asserted with a frame in between to force new color-correction settings to take effect. 14 0x0001 auto exposure enables auto exposure. 13 0x0001 defect correction enables on-the-fly defect correction. 12 0x0000 clip aperture correction clips aperture corrections. small aperture corrections (<8) are attenuated to reduce noise amplification. 11 0x0000 not used not used. 10 0x0001 lens shading correction enables lens shading correction. 9:8 0x0000 reserved 7 0x0000 ae flicker control enable enables flicker control. 6 0x0000 enable the interpolator in 2d defect correction this bit should be set to a 1 when operating in the interlace mode. 5 0x0000 reserved 4 0x0000 bypass color correction matrix bypasses color-correction matrix. 0: normal color processing. 1: outputs raw color bypassing color correction. 3:2 0x0003 ae back light control auto exposure back light compensation control. 00: auto exposure sampling window is specified by r38:2 and r39:2 (large window). 01: auto exposure sampling window is specified by r43:2 and r44:2 (small window). 1x: auto exposure sampling window is specified by the weighted sum of the large window and the small window, with the small window weighted four times more heavily. (where x = 0 or 1). 1 0x0001 enables auto white balance enables auto white balance. 0: freezes white balance at current values. 1: enables auto white balance. 0 0x0000 reserved reserved for future expansion. this register specifies the operating mode of the ifp. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 53 ?2006 aptina imaging corporation all rights reserved. r8:1 r0x108 15:0 0x0080 output format control (r/w) 15:11 0x0000 reserved reserved for future expansion. 10 0x0000 gate pixclk 0: pixclk not gated 1: pixclk gated with line_valid 9 0x0000 flip bayer column flip bayer columns in processed bayer output mode. 0: column order is green, red and blue, green. 1: column order is red, green and green, blue. 8 0x0000 flip bayer row flip bayer row in processed bayer output mode. 0: first row contains green and red; the second row contains blue and green. 1: first row contains blue and green; the second row contains green and red. 7 0x0001 ctls ccir656 protection bits controls the values used for the protection bits in rec. itu-r bt.656 codes. 0: use zeros for the protection bits. 1: use the correct values. 6xreserved 5 0x0000 multiplex y[ycbcr] or g[rgb] multiplexes y (in ycbcr mode) or green (in rgb mode) channel on all channels (monochrome). 0: normal operation 1: forces y or g onto all channels. 4 0x0000 disable cb disables cb color output channel (cb = 128) in ycbcr mode and disables the blue color output channel (b = 0) in rgb mode. 0: normal operation. 1: forces cb to 128 or b to 0. 3 0x0000 disable y disables y color output channel (y = 128) in ycbcr and disables the green color output channel (g = 0) in rgb mode. 0: normal operation. 1: forces y to 128 or g to 0. 2 0x0000 disable cr disables cr color output channel (cr = 128) in ycbcr mode and disables the red color output channel (r = 0) in rgb mode. 0: normal operation. 1: forces cr to 128 or r to 0. 1 0x0000 bayer cfa [vert shift] toggles the assumptions about bayer vertical shift. 0: row containing red comes first. 1: row containing blue comes first. 0 0x0000 bayer cfa [horiz shift] toggles the assumptions about bayer horizontal cfa shift. 0: green comes first. 1: red or blue comes first. this register specifies the output timing and format in conjunction with r0x19b. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 54 ?2006 aptina imaging corporation all rights reserved. r19:1 r0x113 15:0 0x0780 chip level control (r/w) 15:11 x reserved 10 0x0001 din[7:0] and din_clk input enable setting this bit enables din[7:0] and din_clk input pads. this bit can be cleared for floating din[7:0] and din_clk inputs 9 0x0001 din_clk hysteresis enable enable the hysteresis of the din_clk pad in a noisy environment. 8 0x0001 ext_clk hysteresis enable enable the hysteresis of the ext_clk pad in a noisy environment. 7 0x0001 frame_valid odd field to even field level 0: frame_valid drops between even and odd frames. 1: frame_valid remains high between even and odd fields. also line_valid drops when frame_valid is high. this ensures that the 243 active lines of each field (even and odd) can be identified by line_valid = frame_valid = 1. 6 0x0000 inv_f invert the f bit in the 656 generated bit stream. 5xreserved 4 0x0000 select din_clk 0: select the internal 2x pixel clock as the clock for latching the din[7:0] data. 1: select the external din_clk as the clock for latching the din[7:0] data. 3 0x0000 din sample edge 0: use the positive edge of the muxed (din_clk/internal 2x pixel clock) to latch the din[7:0] data. 1: use the negative edge. 2 0x0000 tv encoder select ext dsp 0: tv encoder selects the internal soc output as its input data. 1: tv encoder selects the data from external din[7:0] port as its input data. 1:0 0x0000 dout[7:0] select 00: ccir656 data stream (interlaced) is selected. dout[7:0] = ccir656 data. dout_lsb[1:0] = 0x0. 01: reserved 10: soc colorpipe output is selected. 11: reserved controls several chip level input/output parameters r21:1 r0x115 15:0 0x0000 invert latched pins (r/w) 15:3 x reserved 2 0x0000 xored with the latched pedestal the pedestal pin status latched in r30:1 is xored with this bit before it is used. software uses this bit to enable or disable the pedestal. 1 0x0000 xored with the latched horiz_flip the horiz_flip pin status latched in r30:1 is xored with this bit before it is used. software uses this bit to flip the image on the horizontal axis. 0 0x0000 xored with the latched ntsc_pal_sel the ntsc_pal_sel pin status latched in r30:1 is xored with this bit before it is used. software uses this pin to switch between ntsc and pal. the status of pins (pedestal, horiz_flip, ntsc_pal_sel) are latched at reset into r30:1. bits in r30:1 are xored with this register (r21:1) before they are used. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 55 ?2006 aptina imaging corporation all rights reserved. r29:1 r0x11d 15:0 0x2000 lvds control register (r/w) 15:14 x reserved 13 0x0001 lvds power down when this bit is set or the pad lvds_enable is low or if the pad standby is set, the lvds output is disabled. 12 0x0000 pll test enable 0: normal operation. 1: enable testing the pll in the lvds module. 11 0x0000 lvds test enable 0: normal operation. 1: lvds start and stop bits are replaced with r29:1[10] (lvds_testdata), lvds data is replaced with r29:1[9:0] (lvds_data). 10 0x0000 lvds_testdata when r29:1[11] (lvds_test) is 1, lvds start and stop bits are replaced with this bit. 9:0 0x0000 lvds test data when r29:1[11] (lvds_test) is 0, normal data is sent to the lvds. when r29:1[11] is 1, the value of this field is sent to the lvds. this is used for debugging/testing the lvds module. r30:1 r0x11e 15:0 0x0004 latched pin status (ro) 15:3 x reserved 2 ro pedestal pedestal pin latched during reset. 1rohoriz_flip horiz_flip pin latched at reset. 0rontsc_pal_sel ntsc_pal_sel pin latched at reset. this register is used to latch the pedestal, horiz_flip, ntsc_pal_sel pin status during reset and is accessible (ro) through the two-wire serial interface. r37:1 r0x125 15:0 0x0005 color saturation control (r/w) 15:6 x reserved 5:3 0x0000 overall attenuation of saturation specify overall attenuation of the color saturation. 000: full color saturation 001: 75% of full saturation 010: 50% of full saturation 011: 37.5% of full saturation 100: 25% of full saturation 101: 150% of full saturation 110: black and white 2:0 0x0005 reserved this register specifies the color saturation control settings. r52:1 r0x134 15:0 0x0010 luma offset [can be used to control brightness] (r/w) 15:8 0x0000 offset in rgb mode offset in rgb mode 7:0 0x0010 y offset in ycbcr mode y offset in ycbcr mode offset added to the luma prior to output. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 56 ?2006 aptina imaging corporation all rights reserved. r53:1 r0x135 15:0 0xf010 luma clip (r/w) 15:8 0x00f0 upper limit highest value of output luma. 7:0 0x0010 lower limit lowest value of output luminance. clipping limits for output luma. r59:1 r0x13b 15:0 0x0416 black subtraction (r/w) 15:11 x reserved 10 0x0001 enables subtraction of bl- enables subtraction of black level negative offset from the signal, before lens shading correction. 0: no black level subtraction performed. 1: subtraction enabled. 9:0 0x0016 black level minus offset [bl-] black level negative offset. set this value to row noise constant, r48:0 [9:0], the black level in the signal from the sensor core. the first block of the ifp subtra cts black level negative offset from the sensor core signal. the objective is to remove any pedestal before lens shading correction and auto exposure digital gains. defines and enables black level negative offset. controls reduction of the black level in the signal from the sensor core befor e lens shading correction auto exposure digital gains. r60:1 r0x13c 15:0 0x0400 black addition (r/w) 15:11 x reserved 10 0x0001 enables addition of black level plus offset (bl+) enables addition of black level positive offset to the lens shading corrected signal. 0: no addition performed. 1: addition enabled. 9:0 0x0000 black level positive offset [bl+] this value is added to each pixel value, after lens shading correction and auto exposure digital gains. black level positive can be used to raise the black level subsequent ifp processing. defines and enables black level positive offset. controls raising the black level in the signal after lens shading correction a nd auto exposure digital gains. r72:1 r0x148 15:0 0x0000 test pattern generator control (r/w) 15:8 x reserved 7 0x0000 1: force white balance digital gains to 1.0 0: normal operation. 1: forces white balance digital gains to 1.0 (disable digital gains). 6:3 x reserved 2:0 0x0000 test pattern at the beginning of ifp test pattern at the beginning of ifp. this register enables test pattern generation at the input of the image processor. values greater than 0 turn on the test pattern generator. 0: select the sensor image. 1 to 6: the brightness of the flat color areas depends on the value programmed (from 1 to 6) in this register. 7: produces the color bar pattern. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 57 ?2006 aptina imaging corporation all rights reserved. r128:1 r0x180 15:0 0x0003 lens correction control (r/w) 15:7 x reserved 6 0x0000 reserved this bit is unused. this bit is reserved for future use. 5 0x0000 reserved this bit is unused. this bit is reserved for future use. 4:2 0x0000 kxy scaling the coefficient, kp or kxy, of the cross-term. a 3-bit code determines the value of kp. 000: 0 001: 1 010: 2 011: 4 100: 8 others: 8 1:0 0x0003 kx; ky the scaling factor, kd or kx, for derivative or knee values. a two-bit code determines the value of kd: 00: 1 01: 0.5 10: 0.25 11: 0.125 defines the scaling factor and the cross-term coefficient for lens shading correction. r129:1 r0x181 15:0 0xed05 lens vertical red knee 0 and initial value (r/w) 15:8 0x00ed red vertical knee pt 0 value of red vertical derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the vertical term of the red compensation function. 7:0 0x0005 red vertical initial value initial value of red vertical function. initial value of the vertical term of the red compensation function. initial values are unsigned, positive. knee values are in two's complement representation, for example, 0xff is equivalent to - 1, toggling all bits, then adding 1. r130:1 r0x182 15:0 0x0edc lens vertical red knees 2 and 1 (r/w) 15:8 0x000e red vertical knee pt 2 value of red vertical derivative at vertex (knee) 2. value at vertex 2 value of the piecewise linear derivative of the vertical term of the red compensation function. 7:0 0x00dc red vertical knee pt 1 value of red vertical derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the vertical term of the red compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r131:1 r0x183 15:0 0xef09 lens vertical red knees 4 and 3 (r/w) 15:8 0x00ef red vertical knee pt 4 value of red vertical derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the vertical term of the red-compensation function. 7:0 0x0009 red vertical knee pt 3 value of red vertical derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the vertical term of the red compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 58 ?2006 aptina imaging corporation all rights reserved. r132:1 r0x184 15:0 0xed05 lens vertical green knee 0 and initial value (r/w) 15:8 0x00ed green vertical knee pt 0 value of green vertical derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the vertical term of the green compensation function. 7:0 0x0005 green vertical initial value initial value of green vertical function. initial value of the vertical term of the green compensation function. initial values are unsigned, positive. knee values are in two's complement representation, for example, 0xff is equivalent to -1. r133:1 r0x185 15:0 0x0edc lens vertical green knees 2 and 1 (r/w) 15:8 0x000e green vertical knee pt 2 value of green vertical derivative at vertex (knee) 2. value, at vertex 2, of the piecewise linear derivative of the vertical term of the green compensation function. 7:0 0x00dc green vertical knee pt 1 value of green vertical derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the vertical term of the green compensation function. knee (vertex) values are in two's compliment representation, for example, 0xff is equivalent to -1. r134:1 r0x186 15:0 0xef09 lens vertical green knees 4 and 3 (r/w) 15:8 0x00ef green vertical knee pt 4 value of green vertical derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the vertical term of the green compensation function. 7:0 0x0009 green vertical knee pt 3 value of green vertical derivative of vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the vertical term of the green compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r135:1 r0x187 15:0 0xed05 lens vertical blue knee 0 and initial value (r/w) 15:8 0x00ed blue vertical knee pt 0 value of blue vertical derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the vertical term of the blue compensation function. 7:0 0x0005 blue vertical initial value initial value of blue vertical function. initial value of the vertical term of the blue compensation function. initial values are unsigned, positive. knee values are in two's complement representation, for example, 0xff is equivalent to -1. r136:1 r0x188 15:0 0x0edc lens vertical blue knees 2 and 1 (r/w) 15:8 0x000e blue vertical knee pt 2 value of blue vertical derivative at vertex (knee) 2. value, at vertex 2, of the piecewise linear derivative of the vertical term of the blue compensation function. 7:0 0x00dc blue vertical knee pt 1 value of blue vertical derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the vertical term of the blue compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 59 ?2006 aptina imaging corporation all rights reserved. r137:1 r0x189 15:0 0xef09 lens vertical blue knees 4and 3 (r/w) 15:8 0x00ef blue vertical knee pt 4 value of blue vertical derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the vertical term of the blue compensation function. 7:0 0x0009 blue vertical knee pt 3 value of blue vertical derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the vertical term of the blue compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r138:1 r0x18a 15:0 0xe809 lens horizontal red knee 0 and initial value (r/w) 15:8 0x00e8 red horizontal knee pt 0 value of red horizontal derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the horizontal term of the red compensation function. 7:0 0x0009 red horizontal initial value initial value of red horizontal function. initial value of the horizontal term of the red compensation function. initial values are unsigned, positive. knee values are in two's co mplement representation, for example, 0xff is equivalent to - 1. r139:1 r0x18b 15:0 0xf8f4 lens horizontal red knees 2 and 1 (r/w) 15:8 0x00f8 red horizontal knee pt 2 value of red horizontal derivative at vertex (knee) 2. value, at vertex 2, of the piecewise linear derivative of the horizontal term of the red compensation function. 7:0 0x00f4 red horizontal knee pt 1 value of red horizontal derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the horizontal term of the red compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r140:1 r0x18c 15:0 0xeff4 lens horizontal red knees 4 and 3 (r/w) 15:8 0x00ef red horizontal knee pt 4 value of red horizontal derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the horizontal term of the red compensation function. 7:0 0x00f4 red horizontal knee pt 3 value of red horizontal derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the horizontal term of the red compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r141:1 r0x18d 15:0 0x0002 lens horizontal red knee 5 (r/w) 15:8 x reserved 7:0 0x0002 red horizontal knee pt 5 value of red horizontal derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the horizontal term of the red compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r142:1 r0x18e 15:0 0xe809 lens horizontal green knee 0 and initial value (r/w) 15:8 0x00e8 green horizontal knee pt 0 value of green horizontal derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the horizontal term of the green compensation function. 7:0 0x0009 green horizontal initial value initial value of green horizontal function. initial value of the horizontal term of the green compensation function. initial values are unsigned, positive. knee values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 60 ?2006 aptina imaging corporation all rights reserved. r143:1 r0x18f 15:0 0xf8f4 lens horizontal green knees 2 and 1 (r/w) 15:8 0x00f8 green horizontal knee pt 2 value of green horizontal derivative at vertex (knee) 2. value, at vertex 2, of the piecewise linear derivative of the horizontal term of the green compensation function. 7:0 0x00f4 green horizontal knee pt 1 value of green horizontal derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the horizontal term of the green compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r144:1 r0x190 15:0 0xeff4 lens horizontal green knees 4 and 3 (r/w) 15:8 0x00ef green horizontal knee pt 4 value of green horizontal derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the horizontal term of the green compensation function. 7:0 0x00f4 green horizontal knee pt 3 value of green horizontal derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the horizontal term of the green compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r145:1 r0x191 15:0 0x0002 lens horizontal green knee 5 (r/w) 15:8 x reserved 7:0 0x0002 green horizontal knee pt 5 value of green horizontal derivative at vertex (knee) 5. value, at vertex 5, of the piecewise linear derivative of the horizontal term of the green compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r146:1 r0x192 15:0 0xe809 lens horizontal blue knee 0 and initial value (r/w) 15:8 0x00e8 blue horizontal knee pt 0 value of blue horizontal derivative at vertex (knee) 0. value, at vertex 0, of the piecewise linear derivative of the horizontal term of the blue compensation function. 7:0 0x0009 blue horizontal initial value initial value of blue horizontal function. initial value of the horizontal term of the blue compensation function. initial values are unsigned, positive. knee values are in two's complement representation, for example, 0xff is equivalent to -1. r147:1 r0x193 15:0 0xf8f4 lens horizontal blue knees 2 and 1 (r/w) 15:8 0x00f8 blue horizontal knee pt 2 value of blue horizontal derivative at vertex (knee) 2. value, at vertex 2, of the piecewise linear derivative of the horizontal term of the blue compensation function. 7:0 0x00f4 blue horizontal knee pt 1 value of blue horizontal derivative at vertex (knee) 1. value, at vertex 1, of the piecewise linear derivative of the horizontal term of the blue compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r148:1 r0x194 15:0 0xeff4 lens horizontal blue knees 4 and 3 (r/w) 15:8 0x00ef blue horizontal knee pt 4 value of blue horizontal derivative at vertex (knee) 4. value, at vertex 4, of the piecewise linear derivative of the horizontal term of the blue compensation function. 7:0 0x00f4 blue horizontal knee pt 3 value of blue horizontal derivative at vertex (knee) 3. value, at vertex 3, of the piecewise linear derivative of the horizontal term of the blue compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 61 ?2006 aptina imaging corporation all rights reserved. r149:1 r0x195 15:0 0x0002 lens horizontal blue knee 5 (r/w) 15:8 x reserved 7:0 0x0002 blue horizontal knee pt 5 value of blue horizontal derivative at vertex (knee) 5. value, at vertex 5, of the piecewise linear derivative of the horizontal term of the blue compensation function. knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r153:1 r0x199 15:0 0x0050 line counter (ro) use line counter to determine the number of the line currently being output. r154:1 r0x19a 15:0 0x01a7 frame counter (ro) use frame counter to determine the index of the frame currently being output. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 62 ?2006 aptina imaging corporation all rights reserved. r155:1 r0x19b 15:0 0x0200 output format control 2 (r/w) 15 x reserved 14 0x0000 output processed bayer output processed bayer data. 13 0x0000 debug flicker luma reserved. 12 0x0000 soc as sensor stand-alone mode sensor output coupled directly to soc camera port, including two extra lsb pins to provide access to the full 10-bit sensor output. bits [9:2] of the sensor output are mapped to dout[7:0]. bits [1:0] of the sensor output are mapped to dout_lsb1 and dout_lsb0, respectively. 11 0x0000 ccir656 codes enables embedding rec. itu-r bt.656 synchronization codes to the output data. 10 0x0000 bypass ip entire image processing is bypassed and raw bayer is output directly. in ycbcr or rgb mode: 0: normal operation, sensor core data flows through ifp. 1: bypass ifp and output imager data directly (full 10 bits). the image data still passes through the camera interface fifo and the 10 bits are formatted to two output bytes through the camera interface; that is, 8+2. data rate is effectively the same as default 16-bits /per pixel modes. auto exposure, awb, and other features still function and control the sensor, though they are assuming some gain or correction through the colorpipe. 9 0x0001 invert output pixel clock by default, this bit is asserted and data is launched off the fa lling edge of pixclk for capture by the receiver on the rising edge. 8 0x0000 enable rgb output 0: output ycbcr data. 1: output rgb format data as defined by r155:1[7:6]. 7:6 0x0000 rgb output format 00: 16-bit rgb565. 01: 15-bit rgb555 10: 12-bit rgb444x. 11: 12-bit rgbx444. 5:4 0x0000 test pattern at the end of ifp (ramp) 00: off. 01: by column. 10: by row. 11: by frame. 3 0x0000 reserved 2 0x0000 reserved 1 0x0000 swap bytes in ycbcr mode, swaps c and y bytes. in rgb mode, swaps odd and even bytes. 0 0x0000 swap channels in ycbcr mode, swaps cb and cr channels. in rgb mode, swaps r and b channels. output format control 2 table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 63 ?2006 aptina imaging corporation all rights reserved. r157:1 r0x19d 15:0 0x24ae defect correction control (r/w) 15 x reserved 14:8 0x0024 reserved reserved. 7:5 0x0005 relative threshold relative threshold for defect detection. 4:0 0x000e absolute threshold absolute threshold for defect detection. defect correction control. r167:1 r0x1a7 15:0 0x0280 reducer horizontal output size resize (r/w) 15:11 x reserved 10:0 0x0280 horiz size of output image x size. controls reducer horizontal output size. r170:1 r0x1aa 15:0 0x00f0 reducer vertical output size resize (r/w) 15:11 x reserved 10:0 0x00f0 vert size of output image y size. controls reducer vertical output size. r175:1 r0x1af 15:0 0x0800 reducer zoom control (r/w) 15:12 x reserved 11 0x0001 en_expand 0: display 640 pixels per line 1: enable the line expander to interpolate the input image lines from 642 pixels per line to 720 pixels per line for the ntsc and pal modes of operation. 10 x reserved 9 0x0000 reserved 8 0x0000 reserved 7xreserved 6 0x0000 reserved 5 0x0000 reserved 4 0x0000 reserved 3 0x0000 reserved 2xreserved 1 0x0000 reserved 0 0x0000 reserved r175:1[11] controls horizontal expansion for ntsc and pal. r182:1 r0x1b6 15:0 0x0000 lens vertical red knees 6 and 5 (r/w) 15:8 0x0000 red vertical knee pt 6 7:0 0x0000 red vertical knee pt 5 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r183:1 r0x1b7 15:0 0x0000 lens vertical red knees 8 and 7 (r/w) 15:8 0x0000 red vertical knee pt 8 7:0 0x0000 red vertical knee pt 7 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 64 ?2006 aptina imaging corporation all rights reserved. r184:1 r0x1b8 15:0 0x0000 lens vertical green knees 6 and 5 (r/w) 15:8 0x0000 green vertical knee pt 6 7:0 0x0000 green vertical knee pt 5 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r185:1 r0x1b9 15:0 0x0000 lens vertical green knees 8 and 7 (r/w) 15:8 0x0000 green vertical knee pt 8 7:0 0x0000 green vertical knee pt 7 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r186:1 r0x1ba 15:0 0x0000 lens vertical blue knees 6 and 5 (r/w) 15:8 0x0000 blue vertical knee pt 6 7:0 0x0000 blue vertical knee pt 5 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r187:1 r0x1bb 15:0 0x0000 lens vertical blue knees 8 and 7 (r/w) 15:8 0x0000 blue vertical knee pt 8 7:0 0x0000 blue vertical knee pt 7 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r188:1 r0x1bc 15:0 0x0210 lens horizontal red knees 7 and 6 (r/w) 15:8 0x0002 red horizontal knee pt 7 7:0 0x0010 red horizontal knee pt 6 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r189:1 r0x1bd 15:0 0x020e lens horizontal red knees 9 and 8 (r/w) 15:8 0x0002 red horizontal knee pt 9 7:0 0x000e red horizontal knee pt 8 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r190:1 r0x1be 15:0 0x0017 lens horizontal red knee 10 (r/w) 15:8 x reserved 7:0 0x0017 red horizontal knee pt 10 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r191:1 r0x1bf 15:0 0x0210 lens horizontal green knees 7 and 6 (r/w) 15:8 0x0002 green horizontal knee pt 7 7:0 0x0010 green horizontal knee pt 6 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r192:1 r0x1c0 15:0 0x020e lens horizontal green knees 9 and 8 (r/w) 15:8 0x0002 green horizontal knee pt 9 7:0 0x000e green horizontal knee pt 8 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r193:1 r0x1c1 15:0 0x0017 lens horizontal green knee 10 (r/w) 15:8 x reserved 7:0 0x0017 green horizontal knee pt 10 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r194:1 r0x1c2 15:0 0x0210 lens horizontal blue knees 7 and 6 (r/w) 15:8 0x0002 blue horizontal knee pt 7 7:0 0x0010 blue horizontal knee pt 6 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 65 ?2006 aptina imaging corporation all rights reserved. r195:1 r0x1c3 15:0 0x020e lens horizontal blue knees 9 and 8 (r/w) 15:8 0x0002 blue horizontal knee pt 9 7:0 0x000e blue horizontal knee pt 8 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r196:1 r0x1c4 15:0 0x0017 lens horizontal blue knee 10 (r/w) 15:8 x reserved 7:0 0x0017 blue horizontal knee pt 10 knee (vertex) values are in two's complement representation, for example, 0xff is equivalent to -1. r220:1 r0x1dc 15:0 0x1005 gamma knee y2 and y1 (r/w) 15:8 0x0010 y2 7:0 0x0005 y1 this register specifies output values y1 and y2 for the piecewise linear gamma correction. piecewise linear gamma correction transforms 10-bit luminance from color processing to nonlinear 8-bit luminance to be output from the chip. pre-gamma image processing generates 10-bit luminance values ranging from 0 through 896. piecewise linear gamma correction has 10 linear intervals with knee points corresponding to the following input values: xi = 0 ... 10 = {0, 16, 32, 64, 128, 256, 384, 512, 640, 768, 896}. for each input value xi, the user can program the corresponding output value yi as illustrated in the accompanying text in this table. the valid range for yi is from 0 through 255. a further offset is added to the gamma corrected values as specified in r52:1. default values for gamma table knee points implemented a gamma of 0.6. r221:1 r0x1dd 15:0 0x582f gamma knee y3 and y4 (r/w) 15:8 0x0058 y4 7:0 0x002f y3 this register specifies output values y3 and y4 for the piecewise linear gamma correction. for a description of the gamma correction table, see r220:1. r222:1 r0x1de 15:0 0x9b80 gamma knee y5 and y6 (r/w) 15:8 0x009b y6 7:0 0x0080 y5 this register specifies output values y5 and y6 for the piecewise linear gamma correction. for a description of the gamma correction table, see r220:1. r223:1 r0x1df 15:0 0xc2b0 gamma knee y7 and y8 (r/w) 15:8 0x00c2 y8 7:0 0x00b0 y7 this register specifies output values y7 and y8 for the piecewise linear gamma correction. for a description of the gamma correction table, see r220:1. r224:1 r0x1e0 15:0 0xe0d2 gamma knee y9 and y10 (r/w) 15:8 0x00e0 y10 7:0 0x00d2 y9 this register specifies output values y9 and y10 for the piecewise linear gamma correction. for a description of the gamma correction table, see r220:1. the final output luminance is clamped to y10. r225:1 r0x1e1 15:0 0x0000 gamma knee y0 (r/w) 15:8 x reserved 7:0 0x0000 y0 this register specifies output value y0 corresponding to 0 input of the piecewise linear gamma correction. for a description of the gamma correction table, see r220:1. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga color pipe register descriptionsaddress page 1 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 66 ?2006 aptina imaging corporation all rights reserved. r240:1 r0x1f0 15:0 0x0001 page map (r/w) set camera chip register page. 0: sensor core 1: colorpipe 2: camera control. r241:1 r0x1f1 15:0 0x0000 bytewise addr (r/w) special address to perform 8-bit (instead of 16-bit) reads and writes to the sensor. for additional information, see two- wire serial interface sample on page 96 and appendix a: serial bus description on page 94. table 13: color pipe registeraddress page 1 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 67 ?2006 aptina imaging corporation all rights reserved. camera control register descriptionsaddress page 2 table 14: camera control registeraddress page 2 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name r2:2 r0x202 15:0 0x00ee base matrix signs (r/w) 15:9 x reserved 8 0x0000 k1 (always positive) the sign of k1 is always positive; this bit is always 0. 7 0x0001 sign of k2 6 0x0001 sign of k3 5 0x0001 sign of k4 4 0x0000 k5 (always positive) the sign of k5 is always positive; this bit is always 0. 3 0x0001 sign of k6 2 0x0001 sign of k7 1 0x0001 sign of k8 0 0x0000 k9 (always positive) the sign of k9 is always positive; this bit is always 0. this register specifies the signs of the 9 coefficients in the base color correction matrix. (0 = positive; 1 = negative) r3:2 r0x203 15:0 0x3923 color correction matrices scale codes k1-k5 (r/w) 15 x reserved 14:12 0x0003 scaling of k5 11:9 0x0004 scaling of k4 8:6 0x0004 scaling of k3 5:3 0x0004 scaling of k2 2:0 0x0003 scaling of k1 this register specifies the scaling of coefficients k1 through k5 of the color correction matrices. refer to the description of r9:2 for a detailed description of the color correction matrices used in the soc. the magnitudes of all coefficients are stored as 8 -bit unsigned integers. the scaling scheme accommodates fractional coefficient magnitudes in the range from 0.004 through 15.93. prior to loading, fractional coefficients are multiplied by 16, 32, 64, 128, or 256 and rounded to the nearest integer. for maximum accuracy, the scale factor should be selected so that the scaled coefficient is as close as possible to, but not exceeding, 255. the power of 2 used for scaling in excess of 4 is specified as a 3-bit value in r3:2 and r4:2. the encoding is: 000: scale by 16. 001: scale by 32. 010: scale by 64. 011: scale by 128. 100: scale by 256. a single scale factor is used for the corresponding coefficients in the base and delta matrices. r4:2 r0x204 15:0 0x0724 color correction matrices scale codes k6-k9 (r/w) 15:12 x reserved 11:9 0x0003 scaling of k9 8:6 0x0004 scaling of k8 5:3 0x0004 scaling of k7 2:0 0x0004 scaling of k6 this register specifies the scaling of color correction coefficients k6 through k9 of the color correction matrices. refer to r 3:2 for more details. r9:2 r0x209 15:0 0x00b1 base matrix color correction coefficient k1 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k1.
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 68 ?2006 aptina imaging corporation all rights reserved. r10:2 r0x20a 15:0 0x0033 base matrix color correction coefficient k2 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k2. r11:2 r0x20b 15:0 0x002f base matrix color correction coefficient k3 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k3. r12:2 r0x20c 15:0 0x0080 base matrix color correction coefficient k4 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k4. r13:2 r0x20d 15:0 0x00f0 base matrix color correction coefficient k5 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k5. r14:2 r0x20e 15:0 0x0060 base matrix color correction coefficient k6 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k6. r15:2 r0x20f 15:0 0x0014 base matrix color correction coefficient k7 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k7. r16:2 r0x210 15:0 0x00a4 base matrix color correction coefficient k8 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k8. r17:2 r0x211 15:0 0x00dc base matrix color correction coefficient k9 (r/w) this register specifies the scaled magnitude of the base color correction matrix coefficient k9. r18:2 r0x212 15:0 0x0000 current color correction matrix position (ro) this register specifies the current position of the color correction matrix relative to the original calibration matrices. the matrix position is expressed as a 7-bit number represented in 0.bbbbbbb fixed point format. positions range from 0/128 for red-rich illumination to 127/128 for blue-rich illumination. r19:2 r0x213 15:0 0x008c current awb red channel (ro) this register reports the current value of the red digital gain as an 8-bit number in b.bbbbbbb fixed point format, which range s from 0/128 to 255/128. r20:2 r0x214 15:0 0x009d current awb blue channel (ro) this register reports the current value of the blue digital gain as an 8-bit number in b.bbbbbbb fixed point format, which ranges from 0/128 to 255/128. r21:2 r0x215 15:0 0x0000 delta matrix signs (r/w) 15:9 x reserved 8 0x0000 sign of d1 7 0x0000 sign of d2 6 0x0000 sign of d3 5 0x0000 sign of d4 4 0x0000 sign of d5 3 0x0000 sign of d6 2 0x0000 sign of d7 1 0x0000 sign of d8 0 0x0000 sign of d9 this register specifies the signs of the 9 coefficients of the delta color correction matrix. refer to the description of r9:2 for a detailed description of the color correction matrices used in the soc. r22:2 r0x216 15:0 0x0000 delta matrix color correction coefficient d1 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d1. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r23:2 r0x217 15:0 0x0000 delta matrix color correction coefficient d2 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d2. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 69 ?2006 aptina imaging corporation all rights reserved. r24:2 r0x218 15:0 0x0000 delta matrix color correction coefficient d3 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d3. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r25:2 r0x219 15:0 0x0000 delta matrix color correction coefficient d4 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d4. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r26:2 r0x21a 15:0 0x0000 delta matrix color correction coefficient d5 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d5. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r27:2 r0x21b 15:0 0x0000 delta matrix color correction coefficient d6 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d6. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r28:2 r0x21c 15:0 0x0000 delta matrix color correction coefficient d7 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d7. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r29:2 r0x21d 15:0 0x0000 delta matrix color correction coefficient d8 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d8. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r30:2 r0x21e 15:0 0x0000 delta matrix color correction coefficient d9 (r/w) this register specifies the scaled magnitude of the delta color correction matrix coefficient d9. refer to the description of r 9:2 for a detailed description of the color correction matrices used in the soc. r31:2 r0x21f 15:0 0x00a0 chroma limits (r/w) 15:8 x reserved 7:6 0x0002 relative limit relative test, which compares the magnitudes of the 7-bit chroma to the largest 8-bit rgb component for the pixel: 00: test always passes. 01: chroma < 1/4 max_color. 10: chroma < 1/2 max_color. 11: chroma < max_color. 5:0 0x0020 absolute limit absolute test: both chroma must lie below this value this register controls chroma tests that prevent deeply saturated colors from skewing the white balance statistics. pixels that do not pass these tests are not counted. r32:2 r0x220 15:0 0xc814 awb luma limits (r/w) 15:8 0x00c8 upper limit upper limit of luminance for white balance statistics. 7:0 0x0014 lower limit lower limit of luminance for white balance statistics. to avoid skewing white balance statistics by very dark or very bright values, this register represents the luminance range of pixels to be used for white balance statistics. these limits are 8-bit values represented as 0.bbbbbbbb fixed point format in t he range of 0/256 through 224/256. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 70 ?2006 aptina imaging corporation all rights reserved. r33:2 r0x221 15:0 0x8080 manual wb red and blue gains (r/w) 15:8 0x0080 red gain red channel gain. 7:0 0x0080 blue gain blue channel gain. this register stores the red and blue color channel gains for use when manual white balance is enabled (r6:1[15] is 1). the programmed values represent the desired gains as 8-bit numbers in b.bbbbbbb fixed point format, which range from 0/128 through 255/128. as an example, unity gain has the value 128 (0x80). r34:2 r0x222 15:0 0xd960 red gain awb limits (r/w) 15:8 0x00d9 upper limit upper limit of red channel gain. 7:0 0x0060 lower limit lower limit of red channel gain. this register sets the range of red gain adjustment by the awb algorithm. these limits depend on the normalization of the color correction matrices programmed in r9:2-r17:2 and r22:2-r30:2. to preserve full-range red, a lower limit below 0.75 is not recommended when using default matrices. the 8-bit gain limits are represented in b.bbbbbbb fixed point format. values range from 0/128 through 255/128. r35:2 r0x223 15:0 0xd960 blue gain awb limits (r/w) 15:8 0x00d9 upper limit upper limit of blue channel gain. 7:0 0x0060 lower limit lower limit of blue channel gain. this register sets the range of blue gain adjustment by the awb algorithm. these limits depend on the normalization of the color correction matrices programmed in r9:2-r17:2 and r22:2-r30:2. to preserve full-range blue, a lower limit below 0.75 is not recommended when using default matrices. the 8-bit gain limits are represented in b.bbbbbbb fixed point format. values range from 0/128 through 255/128. r36:2 r0x224 15:0 0x7f00 awb ccm adjustment limits (r/w) 15 x reserved 14:8 0x007f upper limit upper limit of the matrix position. 7xreserved 6:0 0x0000 lower limit lower limit of the matrix position. as described in r18:2, awb determines the best position of the color correction matrix by interpolating between 2 edge matrices: one for red-rich illumination and one for blue-rich illumination. the limits of the matrix position are expressed as 7- bit numbers represented in 0.bbbbbbb fixed point format. positions range from 0/128 for red-rich illumination through 127/ 128 for blue-rich illumination. r38:2 r0x226 15:0 0x8000 auto exposure horizontal window boundaries (r/w) 15:8 0x0080 right boundary 7:0 0x0000 left boundary this register specifies the left and right boundaries of the window used by the ae measurement engine. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the right-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the left-most edge of the frame. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 71 ?2006 aptina imaging corporation all rights reserved. r39:2 r0x227 15:0 0x8008 auto exposure vertical window boundaries (r/w) 15:8 0x0080 bottom boundary 7:0 0x0008 top boundary this register specifies the top and bottom boundaries of the window used by the ae measurement engine. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottom-most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the topmost edge of the frame. r40:2 r0x228 15:0 0xef02 awb advanced control (r/w) 15 0x0001 enable matrix normalization reserved 14 0x0001 reserved 13 0x0001 reserved 12 0x0000 reserved 11 0x0001 reserved 10 0x0001 reserved 9:8 0x0003 reserved 7xreserved 6:3 0x0000 reserved 2:0 0x0002 reserved this register controls the rate of adaptation for the awb algorithm. r41:2 r0x229 15:0 0x8d73 white balance gain wide stability gates (r/w) 15:8 0x008d upper gate 7:0 0x0073 lower gate this register describes the hysteresis window for awb matrix motion. the 8-bit fields contain values in b.bbbbbbb fixed point format, which represent numbers from 0/128 through 255/128. whenever the blue digital gain lies outside this window, it triggers awb to move the color correction matrix toward a position with the blue digital gain near unity. r42:2 r0x22a 15:0 0x00d0 wb zone validity limits (r/w) 15:8 0x0000 min number of open zones required for wb to operate minimum number of zones that must be valid for the set of zones to be considered valid. 7:4 0x000d upper limit upper bound on the hue variation threshold. 3:0 0x0000 low limit lower bound on the hue variation threshold. this register contains three parameters used in the white balance calculation to select regions of interest. the hue variation threshold parameters bound the range within which the hue variation threshold can wander as it attempts to keep the number of valid zones close to, but above, the minimum number of zones specified in the third parameter. this behavior attempts to keep the white balance algorithm focused on the most useful regions of the image while ignoring those that might imbalance the statistics. r43:2 r0x22b 15:0 0x6020 auto exposure horizontal center window boundaries (r/w) 15:8 0x0060 right boundary right window boundary. 7:0 0x0020 left boundary left window boundary. this register specifies the left and right boundaries of the window used by the ae measurement engine in backlight compensation mode. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the right- most edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the leftmost edge of the frame. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 72 ?2006 aptina imaging corporation all rights reserved. r44:2 r0x22c 15:0 0x6020 auto exposure vertical center window boundaries (r/w) 15:8 0x0060 top boundary top window boundary. 7:0 0x0020 bottom boundary bottom window boundary. this register specifies the top and bottom boundaries of the window used by the ae measurement engine in backlight compensation mode. the values programmed in the registers are the fractional percentage, where 128 (decimal) is the bottommost edge of the frame, 64 (decimal) is the middle of the frame, and 0 is the topmost edge of the frame. r45:2 r0x22d 15:0 0x6191 awb window boundaries (r/w) 15:12 0x0006 bottom boundary bottom window boundary (in units of blocks). 11:8 0x0001 top boundary top window boundary (in units of blocks). 7:4 0x0009 right boundary right window boundary (in units of 2 blocks). 3:0 0x0001 left boundary left window boundary (in units of 2 blocks). this register specifies the boundaries of the window used by the wb measurement engine. it describes the window in terms relative to the size of the image: horizontally, in units of 1/10 of the width of the image; vertically, in units of 1/16 of th e height of the image. although the positioning is highly quantized, the window remains roughly in place as the resolution changes. more precisely, the values in the registers are the desired boundaries, in units of square blocks of pixels vertically , and in units of two such blocks horizontally. the size of the blocks is determined by the resolution of the image seen by the white balance measurement engine and is 8x8, 16x16, 32x32, or 64x64 pixels. the block size is the smallest size that can cover the image with no more than 20 blocks horizontally and 16 blocks vertically. using this concept of blocks, the window scales as the image size changes, albeit coarsely. care must be taken when the aspect ratio of the image deviates substantially from that of a full-resolution image, as the horizontal and vertical dimensio ns suggest very different choices of block size. when this happens, the larger block size is selected, leading to greater quantization along one dimension. r46:2 r0x22e 15:0 0x083a auto exposure target and precision control (r/w) 15:8 0x0008 ae stab ility window and range half-size of the ae target luma stability window. 7:0 0x003a luminance value luma value of the ae static target. this register specifies the luma target of the ae algorithm and the size of the window or range around the target in which no ae adjustment is made. this window is centered on target, but the value programmed in the register is 1/2 of the window size. bits r46:2[7:0] have a range of [0-224]. this is target luma that ae is attempting to achieve. bits r46:2[15:8] is the half-width of the window around the target luma that provides hysteresis, that is, ae is considered adapted if the time averaged luma (r77:2) is equal to the value in r46:2[7:0] + or - r46:2[15:8]. warning: make sure that r46:2[7:0] - r46:2[15:8] remains nonnegative. r48:2 r0x230 15:0 0x007b awb red measurement (ro) this register outputs the wb measurement of red in the image. this value is normalized to an arbitrary value that is the same for r48:2, r49:2, and r50:2. only the ratios between these registers are meaningful. r49:2 r0x231 15:0 0x0087 awb luminance measurement (ro) this register outputs the wb measurement of luminance in the image. this value is normalized to an arbitrary value that is the same for r48:2, r49:2, and r50:2. only the ratios between these registers are meaningful. r50:2 r0x232 15:0 0x006d awb blue measurement (ro) this register outputs the wb measurement of blue in the image. this value is normalized to an arbitrary value that is the same for r48:2, r49:2, and r50:2. only the ratios between these registers are meaningful. r52:2 r0x234 15:0 0x0000 auto exposure decision frequency (r/w) auto exposure luma is updated every n frames, where n is given by this register. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 73 ?2006 aptina imaging corporation all rights reserved. r54:2 r0x236 15:0 0xa010 auto exposure gain limits (r/w) 15:8 0x00a0 upper limit upper gain limit. the 8-bit value is in bbbb.bbbb fixed point format. the nominal value is about 1/2 the maximum possible analog gain. 7:0 0x0010 lower limit lower gain limit. the 8-bit value is in bbbb.bbbb fixed point format. the nominal value is 1.0 (0x10). this register specifies upper and lower imager gain limits for the auto exposure algorithm. the values refers to virtual gains rather than the gains that can be programmed in the gains registers of the sensor core (r43:0 to r46:0, r53:0). virtual gains range from 1 to 255, with 16 corresponding to a gai n of 1.0, and 128 corresponding to a gain of 8. virtual gains are mapped into sensor-specific analog gain settings; however the actual feasible gain limits are affected by the range of values that the red to green and blue to green ratios of awb can assume. while the virtual gain setting developed by auto exposure directly controls the green analog gain, the red and blue virtual gains are derived from the gain ratios, and ultimately place a maximum bound on the green gain to avoid out-of-range analog gain values for the red and blue components. the minimum bound on virtual gain can be greater than 1.0 if the sensor needs a minimum signal gain in order to cover the full value range of the sensor's adc. r62:2 r0x23e 15:0 0x1fff ccm adjustment gain threshold (r/w) 15:13 x reserved 12 0x0001 automatic saturation control enable 0: disable automatic color saturation control. 1: enable automatic color saturation control. 11:10 0x0003 reserved 9:8 0x0003 reserved 7:0 0x00ff reserved r63:2 r0x23f 15:0 0x0002 auto exposure current gain zone (ro) this register monitors the current value of the index to the exposure gains table. zone of 0 indicates a bright image, with shutter widths set without regard to flicker abatement. zones 1 through 3 reflect shutter widths that permit full frame rate. zone 4 reflect increasing integration times, with a corresponding decrease in frame rate governed by the inclusive limits set i n r54:2. zone 4 is very low illumination. r76:2 r0x24c 15:0 0x3c80 auto exposure current luma monitor (ro) the value of this register is the normalized sum of pre-gamma corrected luma samples, as determined by the ae backlight compensation field of the mode control register (r6:1, bits [3:2]). the format of this register is fixed point bbbbbbbb.bbbbbbbb, with a range of [0.0, 224.0]. r77:2 r0x24d 15:0 0x003b auto exposure time averaged luma monitor (ro) the value of this register is the time-averaged normalized sum of all the pre-gamma corrected luma samples (time-averaged luma), as determined by the ae backlight compensation field of the mode control register (r6:1, bits[3:2]). however, when the time-averaged luma moves outside the luma target range, the time averaging is disabled and this registers value becomes identical to that of r76:2[15:9]. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 74 ?2006 aptina imaging corporation all rights reserved. r91:2 r0x25b 15:0 0x8002 flicker control (r/w) 15 ro reserved 14:3 x reserved 2 0x0000 reserved 1 0x0001 manual 50/60 when in manual flicker mode (r91:2[0] = 1), defines which flicker frequency to avoid. 0: 50hz 1: 60hz 0 0x0000 auto/manual primary flicker control register. r94:2 r0x25e 15:0 0x7845 base sensor core gain ratios (r/w) 15:8 0x0078 b ratio base blue/green ratio = (bluegain/greengain (right) + bluegain/greengain (left)) / 2. 7:0 0x0045 r ratio base red/green ratio = (redgain/greengain (right) + redgain/greengain (left)) / 2. this register specifies the magnitudes of the base imager core analog gain ratios used during the calibration of the edge color correction matrices. as with the color correction matrix coefficients, the base ratios are the average of the ratios at the ext reme calibration points. they are 8-bit numbers represented in bb.bbbbbb fixed point format. they are always positive. r95:2 r0x25f 15:0 0x4e27 delta sensor core gain ratios (r/w) 15:8 0x004e b ratio delta blue/green ratio = bluegain/greengain (right) - bluegain/greengain (left). 7:0 0x0027 r ratio delta red/green ratio = redgain/greengain (right) - redgain/greengain (left). this register specifies the magnitudes of the imager core analog gain ratio deltas derived from the calibration of the edge col or correction matrices. as with the color correction matrix coefficients, the gain ratio deltas are the differences between the sensor gain ratios at the blue-rich and red-rich extreme calibration points. they are 8-bit numbers represented in bb.bbbbbb fixed point format. their signs are stored in r96:2. r96:2 r0x260 15:0 0x0002 delta sensor core gain ratio signs (r/w) 15:2 x reserved 1 0x0001 sign delta b sign of the delta of the blue to green imager core analog gain ratios. 0 0x0000 sign delta r sign of the delta of the red to green imager core analog gain ratios. this register specifies the signs of the deltas of the imager core analog gain ratios. r97:2 r0x261 15:0 0x9f31 awb analog gain ratios monitor (ro) 15:8 ro blue gain ratio sensor analog gain ratio for blue and green. 7:0 ro red gain ratio sensor analog gain ratio for red and green. this register reflects the current values of the sensor analog gain ratios computed by the awb unit. r98:2 r0x262 15:0 0x1010 auto exposure digital gain monitor (ro) 15:8 ro post lens correction digital gain writable if ae is disabled, otherwise ro. 7:0 ro pre lens correction digital gain writable if ae is disabled, otherwise ro. these digital gains are applied within the ifp. they are independent of the imager gains and writable only when ae is disabled r6:1[14]=0. table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga camera control register descriptionsaddress page 2 pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 75 ?2006 aptina imaging corporation all rights reserved. r101:2 r0x265 15:0 0x0000 auto exposure luma offset (r/w) this value is subtracted from all the pixel values that contribute to current luma (and time averaged luma). the resultant valu e is clamped at 0. the default value of this register should be at least the default value of colorpipe register, r60:1[9-0], if r60:1[10] is set.) r103:2 r0x267 15:0 0x2010 auto exposure digital gain limits (r/w) 15:8 0x0020 post-lens correction digital gain upper limit maximum limit on post-lens correction digital gain. 7:0 0x0010 pre-lens correction digital gain upper limit maximum limit on pre-lens correction digital gain. this register specifies the upper limits of the digital gains used by the ae algorithm. the values programmed into this registe r are in bbbb.bbbb fixed point format. a gain of 1.0 is represented by the value of 16. r240:2 r0x2f0 15:0 0x0002 page map (r/w) set camera chip register page. 0: sensor core. 1: colorpipe. 2: camera control. r241:2 r0x2f1 15:0 0x0000 bytewise addr (r/w) special address to perform 8-bit (instead of 16-bit) reads and writes to the sensor. for additional information, see two- wire serial interface sample on page 96 and appendix a: serial bus description on page 94. r242:2 r0x2f2 15:0 0x0000 awb red and blue gains offsets (r/w) 15:8 0x0000 red gain red channel gain offset. 7:0 0x0000 blue gain offset blue channel gain offset. this register stores the red and blue color channel gain offsets for use when awb is enabled (r6:2[1] = 0). the programmed values should represent the desired gain offsets in 1.7 fixed point format (b.bbbbbbb) (or multiplied by 128). table 14: camera control registeraddress page 2 (continued) 0 = don't care bit, d = r/w (read or write) bit, ? = ro (read only) bit register number bits default name
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 76 ?2006 aptina imaging corporation all rights reserved. modes and timing this section provides an overview of the typical usage modes and related timing infor- mation for the MT9V135. composite video output the analog composite video output is enabled by default and is the main usage mode for the MT9V135. the external pin ntsc_pal_select can be us ed to configure the device for default ntsc or pal operation. this and other vide o configuration settings are available as register settings accessible through the serial interface. for proper ntsc and pal opera- tion, use only default register values. ntsc both differential and single connections of the full ntsc format are supported. the differential connection that uses two output li nes is used for low noise or long distance applications. the single connection is used for pcb tracks and screened cable where noise is not a concern. the ntsc format ha s three black lines at the bottom of each image for padding (which most lcds do not display). pal the pal format is supported with 480 active image rows only. black bars are padded on top and bottom of the image for pal format support. the pal format has 24 black lines at the top and bottom of each image for padding. ntsc or pal with external image processing the on-chip video encoder and dac can be used with external data stream input (d in [7:0] port). correct ntsc or pal format ted ccir656 data is required for correct composite video output. this mode can typically be used together with data output on the parallel d out [7:0] port?for example, for external overlay solutions. single-ended and differential composite output the composite output can be operated in a si ngle-ended or differential mode by simply changing the external resistor configuratio n. for single-ended te rmination, two sche- matics are presented. the first is smpte- compliant; the second is an alternative. for differential mode termination, the first differential schematic; figure 21 on page 78, is smpte-compliant. see figure 19 on page 77 through figure 23 on page 79 for termination schematics. note: the differential schematics have not been tested.
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 77 ?2006 aptina imaging corporation all rights reserved. figure 19: single-ended terminationsmpte compliant figure 20: single-ended termination v dd 75 75 chip boundary i = iplus i = iminus single-ended r=75 r=75 single-ended e.g. pcb track e.g. 75 coax single- ended l = 574 nh l = 574 c = 267 c0 c1 c = 267 l0 l1 l2 typical values for lc 75 terminated receiver r = 15 c = 740 pf l = 2.7 h r0 r2 r3 c2 l3 nh pf pf l = 1.86 h v dd 75 75 chip boundary i = iplus i = iminus single-ended r0 = 75 r1=75 single-ended e.g. pcb track e.g. 75 coax single-ended l = 680 l = 680 c=220 c0 c1 c = 220 l0 l1 l2 typical values for lc 75 terminated receiver nh nh l = 2.2 h pf pf
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 78 ?2006 aptina imaging corporation all rights reserved. figure 21: differential connectionsmpte-compliant figure 22: differential connectiongrounded terminations l = 383 c2 l1 l2 l3 l = 383 c1 l = 383 nh l = 383 nh l4 l5 l6 r2 r = 100.0 outyukn outyukp r10 r11 r = 12.5 r = 12.5 butterworth filter @ 12.825 mhz - 3db (differrential) inyukp inyukn c0 c = 965pf l0 l = 2.07 h r3 r = 37.5 r4 r = 5.75 r1 r = 37.5 r0 r = 5.75 io idc 2/37.5 resonant lift (differrential) nh nh l = 1.24 h l = 1.24 h c = 200 pf c = 200 pf d long 75 twisted pair 75 75 chip boundary p lus differential differential l = 2.2 h l = 680nh l = 680nh c = 220pf c = 220pf c0 c1 l0 l1 l2 r4 r5 c2 5v amp v ref + - ref fb differential to single-ended conversion typical values for lc 75 r0 = 37.5 r1 = 37.5 r2 = 37.5 r3 = 37.5 r6 = 75
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 79 ?2006 aptina imaging corporation all rights reserved. figure 23: differential connectionfloating termination v dd long 75 twisted pair 75 75 chip boundary i = iplus differential differential c0 c1 l0 l1 l2 r4 r5 c2 5v v out amp v ref + - ref fb differential to single-ended conversion typical values for lc 75 terminated rec e minus l = 2.2 h l = 680nh l = 680nh c = 220pf c = 220pf r0 = 37.5 r1 = 37.5 r 2 r7 = 75 r2 = 75
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 80 ?2006 aptina imaging corporation all rights reserved. serial (lvds) output the serial high-speed output port suppo rts the interlaced ccir-656 data format. the lvds port is disabled by default, but can be enabled by the external pin lvd s_ e na b l e. t his p in mu s t be a ss er ted for lv ds to fu nc ti on. lv d s c an be d i sab le d through r0x11d[13]. lvds is also disabled when standby is asserted. the output lvds format is the standard 12-bit package with 10-bit payload format supported by off-the-shelf deserializers, including national (ds92lv1212a), maxim (max9205), and ti (sn65lv1212). an on-chip x12 pll is included for high-speed lvds clock generation. lvds output clock spee d is 324 mhz for ccir support. table 15 describes the lvds packet format; figure 24 on page 80 shows the lvds data format. figure 24: lvds serial output data format notes: 1. each lvds packet contains 12 bits. it starts with a 1 (start bit) and ends with a 0 (stop bit). 2. the 8-bit ccir656-compliant video data byte is shifted out with the lsb bit out first, following the start bit. 3. the lv and the fv bits are sent out following the video data byte. 4. a 12x pll generates the internal shift clock from extclk input. the 8-bit d out [7:0] is concatenated with lv and fv outputs and shifted out through the differential lvds_pos/lvds_neg outputs. 5. refer to table 16 on page 81 for lvds data timing. table 15: lvds packet format 12-bit packet ccir-656 bit[0] 1 (start bit) bit[1] pixeldata[0] bit[2] pixeldata[1] bit[3] pixeldata[2] bit[4] pixeldata[3] bit[5] pixeldata[4] bit[6] pixeldata[5] bit[7] pixeldata[6] bit[8] pixeldata[7] bit[9] lv bit[10] fv bit[11] 0 (stop bit) d1 d0 d3 d2 d5 d4 d7 d6 lv fv internal shift clock lvds serial out start (1) stop (0) ) t dw
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 81 ?2006 aptina imaging corporation all rights reserved. parallel output (d out ) interlaced the d out [7:0] port supports outputting the inte rlaced data stream in a variety of formats, as described in more detail in ?itu-r bt.656 and rgb output? on page 20. figure 25 shows the data that is output on the parallel port for ccir656. both ntsc and pal formats are displayed. the blue values in figure 25 represent ntsc (525/60). the red values represent pal (625/50). figure 25: ccir656 8-bit parallel interface format for 525/60 (625/50) video systems figure 26 shows detailed vertical blanking information for ntsc timing. see table 17 on page 82 for data on field, vertic al blanking, eav, and sav states. figure 26: typical ccir656 vertical blanking intervals for 525/60 video system table 16: serial output data timing values (for extclk = 27 mhz) name minimum typical maximum units t dw 2.5 2.7 3.08 ns f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r y c b y c r y c r y f f 4 4 268 280 4 4 1440 1440 1716 1728 eav code blanking sav code co - sited _ co - sited _ start of digital line start of digital active line next line digital video stream blanking field 1 active video blanking field 2 active video line 4 line 266 line 3 field 1 ( f = 0 ) odd field 2 ( f = 1 ) even eav sav line 1 ( v = 1 ) line 20 ( v = 0 ) line 264 ( v = 1 ) line 283 ( v = 0 ) line 525 ( v = 0 ) h = 1 h = 0
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 82 ?2006 aptina imaging corporation all rights reserved. figure 27 shows detailed vertical blanking information for pal timing. see table 18 for data on field, vertical blanking, eav, and sav states. figure 27: typical ccir656 vertical blanking intervals for 625/50 video system table 17: field, vertical blanking, eav, and sav states line number f v h (eav) h (sav) 1C3 1 1 1 0 4C9 0 1 1 0 20C263 0 0 1 0 264C265 0 1 1 0 266C282 1 1 1 0 283C525 1 0 1 0 table 18: field, vertical blanking, eav, and sav states line number f v h (eav) h (sav) 1C22 0 1 1 0 23C310 0 0 1 0 311C312 0 1 1 0 313C335 1 1 1 0 336C623 1 0 1 0 624C625 1 1 1 0 blanking field 1 active vide o blanking field 2 active vide o field 1 ( f = 0 ) od d field 2 ( f = 1 ) eve n h = 1 eav h = 0 sa v blankin g line 1 ( v = 1 ) line 23 ( v = 0 ) line 311 ( v = 1 ) line 336 ( v = 0 ) line 625 ( v = 1 ) line 624 ( v = 1 )
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 83 ?2006 aptina imaging corporation all rights reserved. progressive the d out [7:0] port also supports progressive, raw data output. the on-chip color processor does not support reading out the pi xel array progressivel y, but the raw pixel data can be made available in sensor stand-alone mode. parallel input (d in ) the data-in port allows external ccir656 data to be multiplexed into the ntsc or pal output data. figure 28 shows the timing of the data-in (d in [7:0]) signals. table 19 describes timing values for the parallel input waveform. both mode 0 and mode 1 wave- forms are supported by the MT9V135. figure 28: parallel input data timing waveform notes: 1. the din_clk clock frequency must match the extclk clock frequency. there can be a phase difference between extclk and din_clk, but the frequency must be the same. interlaced modes true interlaced by default, the MT9V135 reads out the image array in a true interlaced fashion where each field maps to the odd and even rows respectively. the color pipe is supplied by a regular bayer pattern data stream due to the ?paired bayer? cfa filters used with the pixel array, as described in ?pix el array structure? on page 11. table 19: parallel input data timing values name min typical max function tdin_clk 36.975 37.0 37.025 din_clk period ts C 18.5 C d in setup time th C 18.5 C d in hold time tdin _ clk ts th d 0 d 1 d 2 d 3 d 4 d 5 d in [7:0] din _ clk mode 0 tdin _ clk ts th d 0 d 1 d 2 d 3 d 4 d 5 d in [7:0] din _ clk mode 1
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 84 ?2006 aptina imaging corporation all rights reserved. mirroring the MT9V135 supports both horizontal and vertical flips, regardless of the output format. horizontal flip, column sequencing re versed, can be enabled by an external pin (horiz_flip) or a register setting (r0x115[1]) . vertical flip can be controlled through a register setting (r0x020[0]). reset, clocks, and standby reset power-up reset is asserted/de-asserted with the reset_bar pin, which is active low. in the reset state, all control registers are set to default values. soft reset is asserted/de-asserted by the two- wire serial interface program. in soft-reset mode, the two-wire serial interface and the register bus are still running. all control registers are reset using default values. see r0x00d. clocks the MT9V135 has three primary clocks: 1. a master clock coming from the extclk signal. 2. a pixel clock using a clock-gated operation running at half frequency of the master clock in sensor stand-alone mode and the same frequency as extclk in soc mode. 3. din_clk that is associated with the parallel d in port. all device clocks are turned off in power- down mode. when the MT9V135 operates in sensor stand-alone mode, the image flow pipeline clocks can be shut off to conserve power. see r0x00d. the sensor core is a master in the system. the sensor core frame rate defines the overall image flow pipeline frame rate. horizontal bl anking and vertical blanking are influenced by the sensor configuration, and are also a fu nction of certain imag e flow pipeline func- tions. the relationship of the primary cl ocks is depicted in figure 29 on page 85. the image flow pipeline typically generates up to 16 bits per pixel?for example, ycbcr or rgb565?but has only an 8-bit port through which to communicate this pixel data. to generate ntsc or pal format images, the sensor core requires a 27 mhz clock.
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 85 ?2006 aptina imaging corporation all rights reserved. figure 29: primary clock relationships standby pin standby is a multipurpose signal that contro ls three functions: low-power standby, the two-wire serial interface device address, and output signal state functions. table 20 shows how standby affects the output signal state. two-wire serial interface address is based on the s addr pin xored with the r0 x 00d[10]; the r0 x 00d[10] default is 0. (see table 31 on page 94 for details). the r0 x 00d[10] is not writable when standby is asserted ?1.? hard standby is asserted or de-asserted on standby, as described in ?power-saving modes? on page 86. table 20: standby effect on the output state standby output enable r0x00d[6] output disable r0x00d[4] standby output state 00 0driven 00 1high-z 10 xdriven x1 xhigh-z 10 bits/pixel 1 pixel/clock 16 bits/pixel 1 pixel/clock 16 bits/pixel (typ) 0.5 pixel/clock colorpipe output interface sensor pixel clock sensor master clock extclk sensor core
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 86 ?2006 aptina imaging corporation all rights reserved. power-saving modes the sensor can be put into the low-power stan dby state by either of the following mech- anisms: ? asserting standby (provided that r0x00d[7] = 0) ? setting r0x00d[3:2] = 01 by performing a re gister write through the serial register interface (r0x00d[2]: analog standby = 1, r0x00d[3]: chip enable = 0) the two methods are equivalent and have the same effect: ? the source of standby is synchronized an d latched. once latched, the full standby sequence is completed even if the source of standby is removed. ? the readout of the current row is completed. ? internal clocks are gated off. ? the analog signal chain and associated cu rrent and voltage sources are placed in a low-power state. the standby state is maintained for as long as the standby source remains asserted. the state of the signal interface while in standby state is shown in table 21 . while in standby, the state of the internal registers is maintained. the sensor continues to respond to accesses through its serial register interface when standby is asserted through a register write, as described above. the serial register interface does not respond when standby mode is entered by asserting the external standby pin. an even lower-power standby state can be achieved by stopping the input clock (extclk) while in standby. if the input clock is stopped, the sensor will not respond to accesses through its two-wire serial register interface. exit from standby must be through the same mechanism as entry to standby. when the standby source is negated: 1. the internal clocks are restarted. 2. the analog circuitry is restored to its normal operating state. 3. the timing and control circuitry perfor ms a restart, equivalent to writing r0x00d[1] = 1. after this sequence has completed, normal op eration is resumed. if the input clock has been stopped during standby it must be restarted before leaving standby. floating inputs the following MT9V135 pins cannot be floated: ?d in [7:0] (tie to gnd if not used) ? din_clk (tie to gnd if not used) ? pedestal?valid for ntsc only, this pin should be pulled low for pal ? lvds enable?this pin must always be pulled high if lvds is used ?s data ?this pin is bidirectional and should not be floated table 21: signal state during standby signal state fv 0 lv 0 pixclk 1 d out [7:0], d out _lsb[1:0] 0
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 87 ?2006 aptina imaging corporation all rights reserved. output data ordering note: pixclk is 27 mhz when extclk is 27 mhz. note: pixclk is 13.5 mhz when extclk is 27 mhz. note: data output rate is 324 mb/s when extclk is 27 mhz. table 22: output data ordering in d out rgb mode mode (swap disabled) byte d7 d6 d5 d4 d3 d2 d1 d0 rgb565 first r7 r6 r5 r4 r3 g7 g6 g5 second g4 g3 g2 b7 b6 b5 b4 b3 rgb555 first 0 r7r6r5r4r3g7g6 second g5 g4 g3 b7 b6 b5 b4 b3 rgb444x first r7 r6 r5 r4 g7 g6 g5 g4 secondb7b6b5b40000 rgbx444 first 0000r7r6r5r4 second g7 g6 g5 g4 b7 b6 b5 b4 table 23: output data ordering in sensor stand-alone mode mode d7 d6 d5 d4 d3 d2 d1 d0 d out_lsb1 dout_lsb0 10-bit output b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 table 24: data ordering in lvds serial mode mode package[0] package[8:1] package[9] package[10] package[11] default start bit 1b1 dout[7:0] line_valid frame_valid stop bit 1b0
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 88 ?2006 aptina imaging corporation all rights reserved. i/o timing digital output by default, the MT9V135 launches pixel data , fv, and lv synchronously with the falling edge of pixclk. the expectation is that the user captures data, fv, and lv using the rising edge of pixclk. the timing diagram is shown in figure 30. as an option, the polarity of the pixclk ca n be inverted from the default. this is achieved by programming r0x19b[9] to ?0.? figure 30: digital output i/o timing note: pixclk may be inverted by programming register r0x19b[9] = 0. table 25: digital output i/o timing t a= ambient = 25c; vdd = 2.5C3.1v signal parameter conditions min typ max unit extclk t extclk_high 17 C 20 ns t extclk_low 17 C 20 ns t extclk_period C 37.0 C ns f extclk max +/- 100 ppm 27 mhz pixclk 1t pixclk_low 14 C 22 ns t pixclk_high 14 C 22 ns t pixclk_period 36.7 37 37.4 ns data[7:0] t extclkr_dout 8 14 18 ns t dout_su 1418.523 ns t dout_ho 1418.523 ns fv/lv t extclkr_fvlv 8 14 18 ns t fvlv_su 14 18.5 23 ns t fvlv_ho 14 18.5 23 ns t dout_su t dout_ho extclk pixclk d out [7:0] frame_valid line_valid t pixclk_high t extclk_high t fvlv_su t fvlv_ho t extclkr_dout t extclkr_fvlv t extclk_low undefined input output output output t extclk_period t pixclk_period t pixclk_low
MT9V135: 1/4-inch system-on-a-chip (soc) vga modes and timing pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 89 ?2006 aptina imaging corporation all rights reserved. figure 31: spectral characteristics rev4 quantum efficiency 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 rev4 blue rev4 green rev4 red quantum efficiency [%] wavelength [nm]
MT9V135: 1/4-inch system-on-a-chip (soc) vga electrical specifications pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 90 ?2006 aptina imaging corporation all rights reserved. electrical specifications notes: 1. v dd , v aa , and vaapix must all be at the same potential to avoid excessive current draw. care must be taken to avoid excessive noise injection in the analog supplies if all three supplies are tied together. 2. customers requiring a similar part with greater temperature range should consider using the mt9v125. table 26: electrical characteristics and operating conditions t a = ambient = 25c; all supplies at 2.8v parameter 1 condition min typ max unit i/o and core digital voltage (v dd )C2.52.83.1v lvds pll voltage C 2.5 2.8 3.1 v video dac voltage C 2.5 2.8 3.1 v analog voltage (v aa )C2.52.83.1v pixel supply voltage (v aapix )C2.52.83.1v leakage current standby, extclk: high or low 10 a imager operating temperature C C40 +85 c storage temperature C C40 +125 c table 27: video dac electrical characteristics t a = ambient = 25c; all supplies at 2.8v parameter condition min typ max unit resolution C 10 C bits dnl single-ended mode C 0.8 1.1 bits inl single-ended mode C 5.7 8.1 bits output local load single-ended mode, output pad (dac_pos) C 75 C single-ended mode, unused output (dac_neg) C 0 C output voltage single-ended mode, code 000h C 0.02 C v single-ended mode, code 3ffh C 1.42 C v output current single-ended mode, code 000h C 0.6 C ma single-ended mode, code 3ffh C 37.9 C ma dnl differential mode C 0.7 1 bits inl differential mode C 1.4 3 bits output local load differential mode per pad (dac_pos and dac_neg) C 37.5 C output voltage differential mode, code 000h, pad dacp C 0.37 C v differential mode, code 000h, pad dacn C 1.07 C v differential mode, code 3ffh, pad dacp C 1.07 C v differential mode, code 3ffh, pad dacn C 0.37 C v output voltage differential mode, code 000h, pad dacp C 0.6 C ma differential mode, code 000h, pad dacn C 37.9 C ma differential mode, code 3ffh, pad dacp C 37.9 C ma differential mode, code 3ffh, pad dacn C 0.6 C ma differential output, mid level differential mode C 0.72 C v supply current estimate C C 55 ma
MT9V135: 1/4-inch system-on-a-chip (soc) vga electrical specifications pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 91 ?2006 aptina imaging corporation all rights reserved. power consumption notes: 1. 10pf nominal. 2. (ntsc or pal) and lvds should not be operated at the same time. table 28: digital i/o parameters t a = ambient = 25c; all supplies at 2.8v signal parameter definitions condition min typ max unit all outputs load capacitance 1 C 30 pf output signal slew 2.8v, 30pf load C 0.72 C v/ns 2.8v, 5pf load C 1.25 C v/ns v oh output high voltage 2.5 2.8 3.1 v v ol output low voltage C0.3 C 0.3 v i oh output high current v dd = 2.8v, v oh = 2.4v 16 C 26.5 ma i ol output low current v dd = 2.8v, v ol = 0.4v 15.9 C 21.3 ma all inputs v ih input high voltage v dd = 2.8v 1.48 C C v v il input low voltage v dd = 2.8v C C 1.43 v i in input leakage current C2 C 2 a signal cap input signal capacitance C 3.5 C pf table 29: power consumption t a = ambient = 25c; all supplies at 2.8v mode sensor (mw) image-flow proc (mw) i/os (mw) 1 dac (mw) lvds (mw) total (mw) active mode 2 60 100 10 150 80 400 standby 0.56
MT9V135: 1/4-inch system-on-a-chip (soc) vga electrical specifications pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 92 ?2006 aptina imaging corporation all rights reserved. ntsc signal parameters notes: 1. black and white levels are referenced to the blanking level. 2. ntsc convention standardized by the ire (1 ire = 7.14mv). 3. encoder contrast setting r0x011 = r0x001 = 0. 4. dac ref = 2.8k , load = 37.5 table 30: ntsc signal parameters t a = ambient = 25c; all supplies at 2.8v parameter conditions min typ max units notes line frequency 15730 15735 15740 hz field frequency 59.00 59.94 60.00 hz sync rise time 120 164 170 ns sync fall time 120 167 170 ns sync width 4.60 4.74 4.80 ?s sync level 37 39.9 43 ire 2, 4 burst level 37 39.7 43 ire 2, 4 sync to setup (with pedestal off) 9.10 9.40 9.40 s sync to burst start 5.00 5.31 5.60 s front porch 1.40 1.40 1.60 s burst width 8.0 8.5 10.0 cycles black level 6.5 7.5 8.5 ire 1, 2, 4 white level 90 100 110 ire 1, 2, 3, 4
MT9V135: 1/4-inch system-on-a-chip (soc) vga packageanddiedimensions pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 93 ?2006 aptina imaging corporation all rights reserved. packageanddiedimensions figure 32: 48-pin clcc package drawing notes: 1. optical center = package center. 2. all dimensions in millimeters. seating plane 4.4 11.43 5.215 5.715 lid material: borosilicate glass 0.55 thickness wall material: alumina ceramic substrate material: alumina ceramic 0.7 thickness 8.8 4.4 5.715 4.84 5.215 0.8 typ 1.75 0.8 typ 8.8 48 1 10.9 0.1 ctr 47x 1.0 0.2 48x r 0.15 48x 0 .40 0.05 11.43 10.9 0.1 ctr lead finish: au plating, 0.50 microns minimum thickness over ni plating, 1.27 microns minimum thickness 2.3 0.2 1.7 first clear pixel optical center 1 c a b optical area optical area: maximum rotation of optical area relative to package edges: 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover glass d : 100 microns a d 0.90 for reference only 1.400 0.125 0.35 for reference only v ctr ?0.20 a b c h ctr ?0.20 a b c image sensor die: 0.675 thickness 0.10 a 0.05 0.2 4x
MT9V135: 1/4-inch system-on-a-chip (soc) vga appendix a: serial bus description pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 94 ?2006 aptina imaging corporation all rights reserved. appendix a: serial bus description registers are written to and read from the MT9V135 through the two-wire serial inter- face bus. the sensor is a serial interface slave controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred in and out of the MT9V135 through the serial data (s data ) line. the s data and sclk lines are pulled up to v dd off-chip by a 1.5k resistor. either the slave or the master device can pull the s data line down?the serial interface protocol dete rmines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? an acknowledge bit ?a no-acknowledge bit ? an 8-bit message ?a stop bit ? the slave device 8-bit address the s addr pin and r0x00d[10] are used to select between two different addresses in case of conflict with another device. if s addr xor r0 x 00d[10] is low, the slave address is 0x90; if s addr xor r0 x 00d[10] is high, the slave address is 0xba. see table 31 below. sequence a typical read or write sequence begins with the master sending a start bit. after the start bit, the master sends the 8-bit slave device address. the last bit of the address determines if the request is a read or a write, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its addr ess by sending an acknowledge bit back to the master. if the request was a write, the master tran sfers the 8-bit register address for where a write should take place. the slave sends an acknowledge bit to indicate that the register address has been received. the master then transfers the data, 8 bits at a time, with the slave sending an ackn owledge bit after each 8 bits. the MT9V135 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are tran sferred, the register address is automatically incremented, so that the next 16 bits are wri tten to the next register address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as foll ows. the master sends the write mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read mode slave address. the master clocks out the register data, 8 bits table 31: two-wire interface id address switching saddr r0x00d[10] two-wire interface address id 00 0x90 0 1 0xba 1 0 0xba 11 0x90
MT9V135: 1/4-inch system-on-a-chip (soc) vga appendix a: serial bus description pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 95 ?2006 aptina imaging corporation all rights reserved. at a time and sends an acknowledge bit after each 8-bit transfer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high. slave address the 8-bit address of a two-wire serial interface device consists of seven bits of address and one bit of direction. a ?0? in the lsb of the address indicates write mode, and a ?1? indi- cates read mode. the write address of the sensor is 0xba; the read address is 0xbb. this applies only when the s addr is set high. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing or the slave when reading) releases the data line, and the receiver signals an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
MT9V135: 1/4-inch system-on-a-chip (soc) vga two-wire serial interface sample pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 96 ?2006 aptina imaging corporation all rights reserved. two-wire serial interface sample write and read sequences (s addr = 1). 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 33. a start bit sent by the master starts the sequence, foll owed by the write address. the image sensor sends an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each 8-bit transfer, the image sensor sends an acknowledge bit. all 16 bits must be written before the register is updated. after 16 bits are transferred, the register address is automatically incremented so that the next 16 bits are written to the next register. the master stops writ ing by sending a start or stop bit. figure 33: write timing to r0x009value 0x0284 16-bit read sequence a typical read sequence is shown in figure 34. the master writes the register address, as in a write sequence. then a start bit and the read address specify that a read is about to occur from the register. the master then clocks out the register data, 8 bits at a time. the master sends an acknowledge bit after each 8- bit transfer. the register address should be incremented after every 16 bits is transferre d. the data transfer is stopped when the master sends a no-acknowledge bit. figure 34: read timing from r0x009; returned value 0x0284 8-bit write sequence to be able to write one byte at a time to th e register, a special register address is added. the 8-bit write is started by writing the upper 8 bits to the desired register, then writing the lower eight bits to the special register address (r0x0f1). the register is not updated sclk s data 0xba address start sto p ack ack ack ack r0x009 0000 0010 1000 0100 sclk s data 0xba address start start stop ack ack ack ack nack r0x009 0xbb address 0000 0010 1000 0100
MT9V135: 1/4-inch system-on-a-chip (soc) vga two-wire serial interface sample pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 97 ?2006 aptina imaging corporation all rights reserved. until all 16 bits have been written. it is not possible to update just half of a register. in figure 35 on page 97, a typical sequence for an 8-bit write is shown. the second byte is written to the special register (r0x0f1). figure 35: write timing to r0x009value 0x0284 8-bit read sequence to read one byte at a time, the same special register address is used for the lower byte. the upper 8 bits are read from the desired register. by following this with a read from the special register (r0x0f1), the lower 8 bits are accessed (figure 36). the master sets the no-acknowledge bits. figure 36: read timing from r0x009; returned value 0x0284 sclk s data 0xba address start sto p ack ack ack ack r0x009 0xba address start ack ack r0x0f1 0000 0010 1000 0100 sclk s data 0xba address start start ack ack ack nack r0x009 0xbb address 0000 0010 sclk s data 0xba address start start stop ack ack ack nack r0x0f1 0xbb address 1000 0100 ? ? ? ? ? ? continued
MT9V135: 1/4-inch system-on-a-chip (soc) vga two-wire serial interface sample pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 98 ?2006 aptina imaging corporation all rights reserved. two-wire serial bus timing the two-wire serial interface operation re quires a certain minimum of master clock cycles between transitions. these are specified below in master clock cycles. figure 37: serial host clock period and duty cycle figure 38: serial host interface start condition timing figure 39: serial host interface stop condition timing note: all timing are in units of master clock cycle. figure 40: serial host interface data timing for write note: s data is driven by an off-chip transmitter. sclk 2 1 sclk 5 s data 4 sclk 5 s data 4 sclk 4 s data 4
MT9V135: 1/4-inch system-on-a-chip (soc) vga two-wire serial interface sample pdf: 4892883360/ source: 7488170424 aptina eserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 99 ?2006 aptina imaging corporation all rights reserved. figure 41: serial host interface data timing for read note: s data is pulled low by the sensor or allowed to be pulled high by a pull-up resistor off-chip. figure 42: acknowledge signal timing after an 8-bit write to the sensor figure 43: acknowledge signal timing after an 8-bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. sclk 5 s data s clk sensor pulls down s data pin 6 s data 3 s clk sensor tri-states s data pin (turns off pull down) 7 s data 6
10 eunos road 8 13-40, singapore post center, singapore 408600 prodmktg@aptina.com www.aptina.com aptina, aptina imaging, digitalclarity, and the aptina logo are the property of aptina imaging corporation all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. MT9V135: 1/4-inch system-on-a-chip (soc) vga revision history pdf: 4892883360/ source: 7488170424 aptina reserves the right to change products or specifications without notice. MT9V135 ds - rev. d 6/10 en 100 ?2006 aptina imaging corporation all rights reserved. revision history rev. d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/21/10 ? updated to non-confidential rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/6/10 ? updated to aptina template ? updated to production status ? updated table 1, ?ordering information,? on page 1 ? updated titles for figure 4 on page 9 and fi gure 32 on page 93 to say 48-pin instead of 44-pin rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/1/07 ? updated figure 32: 48-pin clcc package drawing on page 93 ? converted decimal register numbers to hexadecimal rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/06 ?initial release

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